📄 boot_gfd.s
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;/*****************************************************
; file name : boot.s
; descrition: boot the arm processor
; history: 2003-1-7 15:59 lc create
;*****************************************************/
include hardware_gfd.h
extern main
AREA BOOT, CODE, READONLY
ENTRY ; Mark first instruction to execute
;vector table
bal RST_DO
bal EXTENT_INSTRU
bal SWI_DO
bal ABORT_PREFETCH_DO
bal ABORT_DATA_DO
mov R1, R1 ;reserved exception
bal Irq_Do
mov r0, r0
bal Fiq_Do
;the code for the fiq
;*****************************************************************
; init all the stacks under all CPU mode
;*****************************************************************
RST_DO
EXPORT RST_DO
; ldr sp, =SP_SVC ;init sp_svc
;
; mov RTA, #0xD2 ;chmod to irq and init sp_irq
; msr cpsr_cf, RTA
; ldr sp, =SP_IRQ
;
; mov RTA, #0XD1 ;chomod to fiq and init sp_fiq
; msr cpsr_cf, RTA
; ldr sp, =SP_FIQ
;
; mov RTA, #0XD7 ;chomod to abt and init sp_ABT
; msr cpsr_cf, RTA
; ldr sp, =SP_ABT
;
; mov RTA, #0XDB ;chomod to undf and init sp_UNDF
; msr cpsr_cf, RTA
; ldr sp, =SP_UND
;
; ;chomod to abt and init sp_sys
; mov RTA, #0xDF ;all interrupts disabled
; msr cpsr_cxsf, RTA ;SYSTEM mode, @32-bit code mode
; ldr sp, =SP_SYS
;
; mov RTA, #0XD3 ;chmod to svc modle, CPSR IRQ bit is disable
; msr cpsr_c, RTA
;***************************************************************
; enable CPSR IRQ bit
;***************************************************************
mrs RTA, cpsr
bic RTA, RTA, #0x80 ;set bit7 to zero
msr cpsr_c, RTA
;***************************************************************
; jump to main function
;***************************************************************
IMPORT __main
b __main
;*****************************************************************
;* entry to the interrupt handler
;*****************************************************************
;*****************************************************************
;* *IRQ service handler flow*
;* **********************
;* interrupt prehandler entrance
;* save the registers used in the IRQ model RTA, RTB, RTC
;* save the lr and spsr to the local var
;* read the PLV
;* save the PLV
;* read the INT number,if necessary mask INTC_MSK
;* judge and jump to the interrypt handler entrance
;*
;* the int_handler_entrance
;*
;* restore the reg used in the IRQ modle
;* chang the modle to the SYS mode
;*
;* save the spsr and lr to the sys sp
;* ____________________________________________________one layer
;* save the reg used in the int_handler ;useless
;* ent int
;* open the irq
;* jump to the int_handler
;* close irq
;* jump to the end_int
;*
;* end_int
;* DISABLE IRQ
;*
;* restore the intc_plv. if necessary unmask the INTC_MSK
;* restore reg saved for the int_handler
;* ret_int
;***********************************************************************
Irq_Do
;stmfd sp!, R_ALL_0_12 ;save all the registers
;ldr RTA, =0XFFFFFFFF
stmfd sp!, {r0,r1}
ldr r0, =IRQ_R1
str r1, [r0]
ldmfd sp!, {r0}
ldr r1, =IRQ_R0
str r0, [r1]
add r13, r13, #4 ;//restore the sp_irq top to original irq top
sub r14, r14, #4
mov r0, r14
mrs r1, spsr
orr r1, r1, #0x80
msr cpsr_cxsf, r1 ;//change irq mode into svc
;------------------------------------------------
bic r1, r1, #0x80 ;//clear the irq mask
stmfd sp!, {r0}
stmfd sp!, {r14}
stmfd sp!, {r1}
ldr r0, =IRQ_R1
ldr r1, [r0]
stmfd sp!, {r1}
ldr r1, =IRQ_R0
ldr r0, [r1]
stmfd sp!, {r0}
ldmfd sp!, {r0,r1}
stmfd sp!, {r0-r12} ;//save the registers r0--r12
;-----------------------------;//search the irq vector and jump to isr
;LDR RTA, =LR_IRQ ;save lr to the variable LR_IRQ
;STR LR, [RTA]
;mrs RTC, spsr ;save spsr to the variable SPSR_IRQ
;LDR RTA, =SPSR_IRQ
;str RTC, [RTA]
ldr RTA, =INTC_FNLSTS ;read the interrupt number,if necessary mask INTC_MSK
ldr RLA, [RTA]
;LDR RTC, =0XFFFF ;clear the low 16 bits
;bic RTB, RLA, RTC
LDR RTA, =0XFFFF0200
AND RTB, RLA, RTA
CMP RTB, #INTSRC_RTC ; judges & jump to the INT_HANDLER_ENTRANCE
IMPORT ENT_INT_RTC
beq ENT_INT_RTC
CMP RTB, #INTSRC_DMA
IMPORT ENT_INT_DMA
beq ENT_INT_DMA
CMP RTB, #INTSRC_EMI
IMPORT ENT_INT_EMI
beq ENT_INT_EMI
CMP RTB, #INTSRC_GPT
IMPORT ENT_INT_GPT
beq ENT_INT_GPT
import ENT_INT_USB
CMP RTB, #INTSRC_USB
beq ENT_INT_USB
CMP RTB, #INTSRC_SPI
;IMPORT ENT_INT_SPI
beq ENT_INT_SPI
CMP RTB, #INTSRC_MMC
;IMPORT ENT_INT_MMC
beq ENT_INT_MMC
; CMP RTB, #INTSRC_UART0
; IMPORT ENT_INT_UART0
; beq ENT_INT_UART0
; CMP RTB, #INTSRC_UART1
; IMPORT ENT_INT_UART1
; beq ENT_INT_UART1
CMP RTB, #INTSRC_I2C
beq ENT_INT_I2C
CMP RTB, #INTSRC_AC97
beq ENT_INT_AC97
CMP RTB, #INTSRC_MMA
beq ENT_INT_MMA
CMP RTB, #INTSRC_EXTINT17
beq ENT_INT_EXTINT17
;CMP RTB, #INTSRC_EXTINT16
;beq ENT_INT_EXTINT16
CMP RTB, #INTSRC_EXTINT15
beq ENT_INT_EXTINT15
; CMP RTB, #INTSRC_TP
;CMP RTB, #INTSRC_EXTINT16
; IMPORT ENT_INT_TP
; beq ENT_INT_TP
;ERROR ;IF ERROR PRINT THE ERROR
;IMPORT HA_INTC_ERROR
;BL HA_INTC_ERROR
;SUBS PC, LR, #4
;enter the interrupt but havenot get the interrupt number
;//clear rtc interrupt
ldr r1, =0x10002014
mov r2, #0x01
str r2, [r1]
;//restore the register
ldmfd sp!, {r0-r12}
ldmfd sp!, {r14}
msr cpsr_cxsf, r14
ldmfd sp!, {r14}
ldmfd sp!, {pc}
;=================================================================
;ENT_INT_RTC b ENT_INT_RTC
;ENT_INT_DMA b ENT_INT_DMA
;ENT_INT_EMI b ENT_INT_EMI
;ENT_INT_GPT b ENT_INT_GPT
;ENT_INT_USB b ENT_INT_USB
ENT_INT_SPI b ENT_INT_SPI
ENT_INT_MMC b ENT_INT_MMC ;add the ENT_INT_UART1 IN THE HA_IsrUART.c FILE
;ENT_INT_UART0 b ENT_INT_UART0
;ENT_INT_UART1 b ENT_INT_UART1 ;add the ENT_INT_UART1 IN THE HA_IsrUART.c FILE
ENT_INT_I2C b ENT_INT_I2C
ENT_INT_AC97 b ENT_INT_AC97
ENT_INT_MMA b ENT_INT_MMA
ENT_INT_EXTINT17 b ENT_INT_EXTINT17
ENT_INT_EXTINT16 b ENT_INT_EXTINT16
ENT_INT_EXTINT15 b ENT_INT_EXTINT15
; OFFENT_INT_ b OFFENT_INT_
ENT_INT_EXTINT0 b ENT_INT_EXTINT0
ENT_INT_EXTINT1 b ENT_INT_EXTINT1
ENT_INT_EXTINT2 b ENT_INT_EXTINT2
ENT_INT_EXTINT3 b ENT_INT_EXTINT3
ENT_INT_EXTINT4 b ENT_INT_EXTINT4
ENT_INT_EXTINT5 b ENT_INT_EXTINT5
ENT_INT_EXTINT6 b ENT_INT_EXTINT6
ENT_INT_EXTINT7 b ENT_INT_EXTINT7
ENT_INT_EXTINT8 b ENT_INT_EXTINT8
ENT_INT_EXTINT9 b ENT_INT_EXTINT9
ENT_INT_EXTINT10 b ENT_INT_EXTINT10
ENT_INT_EXTINT11 b ENT_INT_EXTINT11
ENT_INT_EXTINT12 b ENT_INT_EXTINT12
ENT_INT_EXTINT13 b ENT_INT_EXTINT13
ENT_INT_EXTINT14 b ENT_INT_EXTINT14
;*****************************************************************
;COMENMT
;IRQ DO END
;*******************************************************************
;***********************************************************
EXTENT_INSTRU
b EXTENT_INSTRU
SWI_DO
stmfd sp!, {r14}
ldmfd sp!, {pc}^
ABORT_PREFETCH_DO
b ABORT_PREFETCH_DO
ABORT_DATA_DO
b ABORT_DATA_DO
;//Irq_Do
;// b Irq_Do
Fiq_Do
b Fiq_Do
;*************************************************************
;;************************************************
;;********************************************************
;********************************************************
;DEFINE THE VARIABLE END
;DATA SECTION
AREA DATA_SECTION, DATA, READWRITE
KEEP
LR_USR DCD 0X0
LR_SYS DCD 0X0
LR_SVC DCD 0X0
LR_IRQ DCD 0X0
LR_FIQ DCD 0X0
LR_UND DCD 0X0
LR_ABT DCD 0X0
SPSR_SVC DCD 0X0
SPSR_IRQ DCD 0X0
SPSR_FIQ DCD 0X0
SPSR_UND DCD 0X0
SPSR_ABT DCD 0X0
INTC_PLV_V DCD 0X0
IRQ_R1 DCD 0X0
IRQ_R0 DCD 0X0
IRQ_TMP DCD 0X0
EXPORT LR_IRQ
EXPORT SPSR_IRQ
;============================================================
;DEFINE THE VARIABLE END
END
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