nand.h

基于一款32位嵌入式微处理器的Nand Flash 接口的测试代码

/*************************************************************************************
*	Copyright (c) 2005 by National ASIC System Engineering Research Center.
*	PROPRIETARY RIGHTS of ASIC are involved in the subject matter of this 
*	material.  All manufacturing, reproduction, use, and sales rights 
*	pertaining to this subject matter are governed by the license agreement.
*	The recipient of this software implicitly accepts the terms of the license.
*
*	File Name: rtc.h
*
*	File Description:
*			The file define some macro definition used in nand.c file.
*		
*	Created by Wuer
**************************************************************************************/

#ifndef Nand_H
#define Nand_H

#include "typedef.h"

/*several macros of nand registers*/

/* Standard NAND flash commands	*/

#define		NAND_CMD_READ0		0x80000000                                     //highesn bit means enable in GIII controller
#define		NAND_CMD_ERASE1		0x80000060
#define		NAND_CMD_STATUS		0x80000070
#define		NAND_CMD_SEQIN		0x80000080
#define		NAND_CMD_RESET		0x800000ff


/* NAND flash relative registers */
#define  EMI_SRAM_REGBASE			 0x11000000 			 	 //Sdram sram register base;
#define  EMI_NAND_REGBASE			 0x11000100 			 	 //NAND FLASH register base;
                                	
#define	 EMIADDR_SMCONF				( EMI_SRAM_REGBASE+0x00 )	 //adress of sram time_sequence register
#define  EMIADDR_CSGBAB				( EMI_SRAM_REGBASE+0x04 )  	 //adress of CSA and CSB chip select register
#define	 EMIADDR_CSGBCD 			( EMI_SRAM_REGBASE+0X08 )	 //adress of CSC and CSD chip select register	
#define	 EMIADDR_CSGBEF				( EMI_SRAM_REGBASE+0Xc  )	  //adress of CSE and CSF chip select register
#define	 EMIADDR_REMAP				( EMI_SRAM_REGBASE+0X10  )	 //Remap register select boot memory
#define	 EMIADDR_SDCONF1			( EMI_SRAM_REGBASE+0X14  )	 //sram and adram time_sequence register I
#define	 EMIADDR_SDCONF2			( EMI_SRAM_REGBASE+0X18  )	 //sram and adram time_sequence register II
                                	
#define	 EMIADDR_NANDADDR			( EMI_NAND_REGBASE+0X00  )	 //adress of Nand Flash adress register
#define	 EMIADDR_NANDCOM			( EMI_NAND_REGBASE+0X04  )	 //adress of Nand Flash control register
#define	 EMIADDR_NANDSTATUS			( EMI_NAND_REGBASE+0X0c  )	 //adress of Nand Flash status register
#define	 EMIADDR_NANDERRORADDR1		( EMI_NAND_REGBASE+0X10  )	 //adress of Nand Flash error register I
#define	 EMIADDR_NANDERRORADDR2		( EMI_NAND_REGBASE+0X14  )	 //adress of Nand Flash error register II                                             
#define	 EMIADDR_NANDCONF			( EMI_NAND_REGBASE+0X18  )	 //adress of Nand Flash config register
#define  EMIADDR_NANDINTR			( EMI_NAND_REGBASE+0X1c  )	 //Int clear
#define  EMIADDR_NANDFINECC			( EMI_NAND_REGBASE+0X20  ) 	 //ECC complish
#define  EMIADDR_NANDIDLE			( EMI_NAND_REGBASE+0X24  ) 	 //Compish register
                                	
#define  EMI_NAND_DATA			 	0x11000200

#define	 EMIADDR_NANDCONF_VAL    0x02200aaa         
													// 4 address 0x1aa3aa      
                                                    //Trr 10 cycles
                                                    //Tclh 2 cycles
                                                    //Talh 2 cycles
                                                    //Twh  3 cycles
                                                    //Read_width 10 cycles
                                                    //Writ_width 10 cycles
                                                                                                       
//config for GE00
   #define GPIO_PH5_DIR	(GPIO_BASE+0X68)
   #define GPIO_PH5_SEL	(GPIO_BASE+0X6C)
   #define GPIO_PH5_DATA	(GPIO_BASE+0X7C)

//config for GE01 and GE02
  #define GPIO_PB9_DIR	(GPIO_BASE+0X10)
  #define GPIO_PB9_SEL	(GPIO_BASE+0X14)
  #define GPIO_PB9_DATA	(GPIO_BASE+0X18)



/* NAND flash operation functions*/


STATUS	ModuleNand(void);

STATUS NandErase(U32 page);
STATUS NandWrite(U32 page, U32 bufferhead);
STATUS NandRead(U32 page, U32 bufferhead);
STATUS check(U32 head1, U32 head2, U32 num);
void init_nand(void);
void emi_handler(void);
void clear(U32 head, U32 num);
void DataDefine(U32 head, char data, U32 num);
#endif