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📄 i2c-pxa.c

📁 i2c 在linux下的驱动设计
💻 C
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	writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));}static void i2c_pxa_slave_stop(struct pxa_i2c *i2c){	if (i2c->msg)		i2c_pxa_master_complete(i2c, I2C_RETRY);}#endif/* * PXA I2C Master mode */static inline unsigned int i2c_pxa_addr_byte(struct i2c_msg *msg){	unsigned int addr = (msg->addr & 0x7f) << 1;	if (msg->flags & I2C_M_RD)		addr |= 1;	return addr;}static inline void i2c_pxa_start_message(struct pxa_i2c *i2c){	u32 icr;	/*	 * Step 1: target slave address into IDBR	 */	writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c));	/*	 * Step 2: initiate the write.	 */	icr = readl(_ICR(i2c)) & ~(ICR_STOP | ICR_ALDIE);	writel(icr | ICR_START | ICR_TB, _ICR(i2c));}/* * We are protected by the adapter bus mutex. */static int i2c_pxa_do_xfer(struct pxa_i2c *i2c, struct i2c_msg *msg, int num){	long timeout;	int ret;	/*	 * Wait for the bus to become free.	 */	ret = i2c_pxa_wait_bus_not_busy(i2c);	if (ret) {		dev_err(&i2c->adap.dev, "i2c_pxa: timeout waiting for bus free\n");		goto out;	}	/*	 * Set master mode.	 */	ret = i2c_pxa_set_master(i2c);	if (ret) {		dev_err(&i2c->adap.dev, "i2c_pxa_set_master: error %d\n", ret);		goto out;	}	spin_lock_irq(&i2c->lock);	i2c->msg = msg;	i2c->msg_num = num;	i2c->msg_idx = 0;	i2c->msg_ptr = 0;	i2c->irqlogidx = 0;	i2c_pxa_start_message(i2c);	spin_unlock_irq(&i2c->lock);	/*	 * The rest of the processing occurs in the interrupt handler.	 */	timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);	/*	 * We place the return code in i2c->msg_idx.	 */	ret = i2c->msg_idx;	if (timeout == 0)		i2c_pxa_scream_blue_murder(i2c, "timeout"); out:	return ret;}/* * i2c_pxa_master_complete - complete the message and wake up. */static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret){	i2c->msg_ptr = 0;	i2c->msg = NULL;	i2c->msg_idx ++;	i2c->msg_num = 0;	if (ret)		i2c->msg_idx = ret;	wake_up(&i2c->wait);}static void i2c_pxa_irq_txempty(struct pxa_i2c *i2c, u32 isr){	u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB); again:	/*	 * If ISR_ALD is set, we lost arbitration.	 */	if (isr & ISR_ALD) {		/*		 * Do we need to do anything here?  The PXA docs		 * are vague about what happens.		 */		i2c_pxa_scream_blue_murder(i2c, "ALD set");		/*		 * We ignore this error.  We seem to see spurious ALDs		 * for seemingly no reason.  If we handle them as I think		 * they should, we end up causing an I2C error, which		 * is painful for some systems.		 */		return; /* ignore */	}	if (isr & ISR_BED) {		int ret = BUS_ERROR;		/*		 * I2C bus error - either the device NAK'd us, or		 * something more serious happened.  If we were NAK'd		 * on the initial address phase, we can retry.		 */		if (isr & ISR_ACKNAK) {			if (i2c->msg_ptr == 0 && i2c->msg_idx == 0)				ret = I2C_RETRY;			else				ret = XFER_NAKED;		}		i2c_pxa_master_complete(i2c, ret);	} else if (isr & ISR_RWM) {		/*		 * Read mode.  We have just sent the address byte, and		 * now we must initiate the transfer.		 */		if (i2c->msg_ptr == i2c->msg->len - 1 &&		    i2c->msg_idx == i2c->msg_num - 1)			icr |= ICR_STOP | ICR_ACKNAK;		icr |= ICR_ALDIE | ICR_TB;	} else if (i2c->msg_ptr < i2c->msg->len) {		/*		 * Write mode.  Write the next data byte.		 */		writel(i2c->msg->buf[i2c->msg_ptr++], _IDBR(i2c));		icr |= ICR_ALDIE | ICR_TB;		/*		 * If this is the last byte of the last message, send		 * a STOP.		 */		if (i2c->msg_ptr == i2c->msg->len &&		    i2c->msg_idx == i2c->msg_num - 1)			icr |= ICR_STOP;	} else if (i2c->msg_idx < i2c->msg_num - 1) {		/*		 * Next segment of the message.		 */		i2c->msg_ptr = 0;		i2c->msg_idx ++;		i2c->msg++;		/*		 * If we aren't doing a repeated start and address,		 * go back and try to send the next byte.  Note that		 * we do not support switching the R/W direction here.		 */		if (i2c->msg->flags & I2C_M_NOSTART)			goto again;		/*		 * Write the next address.		 */		writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c));		/*		 * And trigger a repeated start, and send the byte.		 */		icr &= ~ICR_ALDIE;		icr |= ICR_START | ICR_TB;	} else {		if (i2c->msg->len == 0) {			/*			 * Device probes have a message length of zero			 * and need the bus to be reset before it can			 * be used again.			 */			i2c_pxa_reset(i2c);		}		i2c_pxa_master_complete(i2c, 0);	}	i2c->icrlog[i2c->irqlogidx-1] = icr;	writel(icr, _ICR(i2c));	show_state(i2c);}static void i2c_pxa_irq_rxfull(struct pxa_i2c *i2c, u32 isr){	u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);	/*	 * Read the byte.	 */	i2c->msg->buf[i2c->msg_ptr++] = readl(_IDBR(i2c));	if (i2c->msg_ptr < i2c->msg->len) {		/*		 * If this is the last byte of the last		 * message, send a STOP.		 */		if (i2c->msg_ptr == i2c->msg->len - 1)			icr |= ICR_STOP | ICR_ACKNAK;		icr |= ICR_ALDIE | ICR_TB;	} else {		i2c_pxa_master_complete(i2c, 0);	}	i2c->icrlog[i2c->irqlogidx-1] = icr;	writel(icr, _ICR(i2c));}static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id){	struct pxa_i2c *i2c = dev_id;	u32 isr = readl(_ISR(i2c));	if (i2c_debug > 2 && 0) {		dev_dbg(&i2c->adap.dev, "%s: ISR=%08x, ICR=%08x, IBMR=%02x\n",			__func__, isr, readl(_ICR(i2c)), readl(_IBMR(i2c)));		decode_ISR(isr);	}	if (i2c->irqlogidx < ARRAY_SIZE(i2c->isrlog))		i2c->isrlog[i2c->irqlogidx++] = isr;	show_state(i2c);	/*	 * Always clear all pending IRQs.	 */	writel(isr & (ISR_SSD|ISR_ALD|ISR_ITE|ISR_IRF|ISR_SAD|ISR_BED), _ISR(i2c));	if (isr & ISR_SAD)		i2c_pxa_slave_start(i2c, isr);	if (isr & ISR_SSD)		i2c_pxa_slave_stop(i2c);	if (i2c_pxa_is_slavemode(i2c)) {		if (isr & ISR_ITE)			i2c_pxa_slave_txempty(i2c, isr);		if (isr & ISR_IRF)			i2c_pxa_slave_rxfull(i2c, isr);	} else if (i2c->msg) {		if (isr & ISR_ITE)			i2c_pxa_irq_txempty(i2c, isr);		if (isr & ISR_IRF)			i2c_pxa_irq_rxfull(i2c, isr);	} else {		i2c_pxa_scream_blue_murder(i2c, "spurious irq");	}	return IRQ_HANDLED;}static int i2c_pxa_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num){	struct pxa_i2c *i2c = adap->algo_data;	int ret, i;	/* If the I2C controller is disabled we need to reset it (probably due 	   to a suspend/resume destroying state). We do this here as we can then 	   avoid worrying about resuming the controller before its users. */	if (!(readl(_ICR(i2c)) & ICR_IUE))		i2c_pxa_reset(i2c);	for (i = adap->retries; i >= 0; i--) {		ret = i2c_pxa_do_xfer(i2c, msgs, num);		if (ret != I2C_RETRY)			goto out;		if (i2c_debug)			dev_dbg(&adap->dev, "Retrying transmission\n");		udelay(100);	}	i2c_pxa_scream_blue_murder(i2c, "exhausted retries");	ret = -EREMOTEIO; out:	i2c_pxa_set_slave(i2c, ret);	return ret;}static u32 i2c_pxa_functionality(struct i2c_adapter *adap){	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;}static const struct i2c_algorithm i2c_pxa_algorithm = {	.master_xfer	= i2c_pxa_xfer,	.functionality	= i2c_pxa_functionality,};static struct pxa_i2c i2c_pxa = {	.lock	= SPIN_LOCK_UNLOCKED,	.adap	= {		.owner		= THIS_MODULE,		.algo		= &i2c_pxa_algorithm,		.name		= "pxa2xx-i2c.0",		.retries	= 5,	},};#define res_len(r)		((r)->end - (r)->start + 1)static int i2c_pxa_probe(struct platform_device *dev){	struct pxa_i2c *i2c = &i2c_pxa;	struct resource *res;#ifdef CONFIG_I2C_PXA_SLAVE	struct i2c_pxa_platform_data *plat = dev->dev.platform_data;#endif	int ret;	int irq;	res = platform_get_resource(dev, IORESOURCE_MEM, 0);	irq = platform_get_irq(dev, 0);	if (res == NULL || irq < 0)		return -ENODEV;	if (!request_mem_region(res->start, res_len(res), res->name))		return -ENOMEM;	i2c = kmalloc(sizeof(struct pxa_i2c), GFP_KERNEL);	if (!i2c) {		ret = -ENOMEM;		goto emalloc;	}	memcpy(i2c, &i2c_pxa, sizeof(struct pxa_i2c));	init_waitqueue_head(&i2c->wait);	i2c->adap.name[strlen(i2c->adap.name) - 1] = '0' + dev->id % 10;	i2c->reg_base = ioremap(res->start, res_len(res));	if (!i2c->reg_base) {		ret = -EIO;		goto eremap;	}	i2c->iobase = res->start;	i2c->iosize = res_len(res);	i2c->irq = irq;	i2c->slave_addr = I2C_PXA_SLAVE_ADDR;#ifdef CONFIG_I2C_PXA_SLAVE	if (plat) {		i2c->slave_addr = plat->slave_addr;		i2c->slave = plat->slave;	}#endif	switch (dev->id) {	case 0:#ifdef CONFIG_PXA27x		pxa_gpio_mode(GPIO117_I2CSCL_MD);		pxa_gpio_mode(GPIO118_I2CSDA_MD);#endif		pxa_set_cken(CKEN14_I2C, 1);		break;#ifdef CONFIG_PXA27x	case 1:		local_irq_disable();		PCFR |= PCFR_PI2CEN;		local_irq_enable();		pxa_set_cken(CKEN15_PWRI2C, 1);#endif	}	ret = request_irq(irq, i2c_pxa_handler, IRQF_DISABLED,			  i2c->adap.name, i2c);	if (ret)		goto ereqirq;	i2c_pxa_reset(i2c);	i2c->adap.algo_data = i2c;	i2c->adap.dev.parent = &dev->dev;	ret = i2c_add_adapter(&i2c->adap);	if (ret < 0) {		printk(KERN_INFO "I2C: Failed to add bus\n");		goto eadapt;	}	platform_set_drvdata(dev, i2c);#ifdef CONFIG_I2C_PXA_SLAVE	printk(KERN_INFO "I2C: %s: PXA I2C adapter, slave address %d\n",	       i2c->adap.dev.bus_id, i2c->slave_addr);#else	printk(KERN_INFO "I2C: %s: PXA I2C adapter\n",	       i2c->adap.dev.bus_id);#endif	return 0;eadapt:	free_irq(irq, i2c);ereqirq:	switch (dev->id) {	case 0:		pxa_set_cken(CKEN14_I2C, 0);		break;#ifdef CONFIG_PXA27x	case 1:		pxa_set_cken(CKEN15_PWRI2C, 0);		local_irq_disable();		PCFR &= ~PCFR_PI2CEN;		local_irq_enable();#endif	}eremap:	kfree(i2c);emalloc:	release_mem_region(res->start, res_len(res));	return ret;}static int i2c_pxa_remove(struct platform_device *dev){	struct pxa_i2c *i2c = platform_get_drvdata(dev);	platform_set_drvdata(dev, NULL);	i2c_del_adapter(&i2c->adap);	free_irq(i2c->irq, i2c);	switch (dev->id) {	case 0:		pxa_set_cken(CKEN14_I2C, 0);		break;#ifdef CONFIG_PXA27x	case 1:		pxa_set_cken(CKEN15_PWRI2C, 0);		local_irq_disable();		PCFR &= ~PCFR_PI2CEN;		local_irq_enable();#endif	}	release_mem_region(i2c->iobase, i2c->iosize);	kfree(i2c);	return 0;}static struct platform_driver i2c_pxa_driver = {	.probe		= i2c_pxa_probe,	.remove		= i2c_pxa_remove,	.driver		= {		.name	= "pxa2xx-i2c",	},};static int __init i2c_adap_pxa_init(void){	return platform_driver_register(&i2c_pxa_driver);}static void i2c_adap_pxa_exit(void){	return platform_driver_unregister(&i2c_pxa_driver);}MODULE_LICENSE("GPL");module_init(i2c_adap_pxa_init);module_exit(i2c_adap_pxa_exit);

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