lab_mc_sn-rtl-a.vhd

关于一个Motor Controller示例的E语言验证程序！

Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;


ARCHITECTURE rtl of lab_mc_sn IS 

  COMPONENT  lab_mc
  PORT (
    clk	           : IN	 std_logic;
    reset          : IN	 std_logic;
    speed_now      : IN	 std_logic_vector(12 downto 0);
    target_speed   : IN	 std_logic_vector(12 downto 0);
    min_speed      : IN	 std_logic_vector(12 downto 0);
    pwme           : OUT std_logic
    );
  end COMPONENT; -- lab_mc

  COMPONENT compspec
  END COMPONENT;
    
    signal mc_clk_i            : std_logic := '0';
    signal mc_reset_i	       : std_logic;
    signal mc_speed_now_i      : std_logic_vector(12 downto 0);
    signal mc_target_speed_i   : std_logic_vector(12 downto 0);
    signal mc_min_speed_i      : std_logic_vector(12 downto 0);
    signal mc_pwme_o           : std_logic;    

BEGIN

  SPECMAN: compspec;

  mc_inst: lab_mc
  PORT MAP(
    clk            =>  mc_clk_i          ,
    reset          =>  mc_reset_i	 ,
    speed_now      =>  mc_speed_now_i    ,
    target_speed   =>  mc_target_speed_i ,    
    min_speed      =>  mc_min_speed_i    ,
    pwme           =>  mc_pwme_o      
   ); 
  
 mc_clk_i <= not mc_clk_i after 500 ns;
 
END rtl;