bug_lab_mc-rtl-a.vhd

关于一个Motor Controller示例的E语言验证程序！

library SYNOPSYS;
use SYNOPSYS.attributes.all;
architecture rtl of bug_lab_mc is
--define the signal_structure and flow of the device
signal cnt125: INTEGER range 0 to 124;
signal cnt375: INTEGER range 0 to 374;
signal cnt500: INTEGER range 0 to 499;
signal internal_target : std_logic_vector(12 downto 0);

-- USER DEFINED ENCODED state machine: phase
type phase_type is (phB1, phB2);
attribute enum_encoding of phase_type: type is
	"0 " &		-- phB1
	"1 ";		-- phB2
signal phase: phase_type;
--------------------------------------------

-- USER DEFINED ENCODED state machine: speeding
type speeding_type is (UPA, UPB ,Dn ,final);
attribute enum_encoding of speeding_type: type is
        "00 " &          --UPA
        "01 " &          --UPB
        "10 " &          --Dn
        "11 ";           --final
signal speeding: speeding_type;
-----------------------------------------------

begin
-- concurrent signals assignments
--MotorControl
--internal_target <= target_speed and TO_STDLOGICVECTOR(BIT_VECTOR'(b"1_1111_1100_0000")) ;
internal_target <= target_speed ;
peeding_machine: process (reset,clk)
begin
   if reset='1' then
      speeding <= UPA;
   elsif (clk'event and clk='1') then
      case speeding is
           when UPA =>
              if (speed_now = internal_target) then
    			  speeding <= final;
		      elsif (speed_now > internal_target) then
			     speeding <= Dn;
		      elsif (speed_now < min_speed) then
			     speeding <= UPA;
		      elsif (speed_now >=min_speed) and (speed_now < internal_target) then
			     speeding <= UPB;
		      end if;
		      
  	   when UPB =>
	  	      if (speed_now = internal_target) then
    			  speeding <= final;
		      elsif (speed_now < min_speed) then
			     speeding <= UPA;
		      elsif (speed_now >=min_speed) and (speed_now < internal_target) then
			     speeding <= UPB;
		      elsif (speed_now > internal_target) then
			     speeding <= Dn;
		      end if;
		      
	   when Dn =>
             if (speed_now = internal_target) then
    			 speeding <= final;
		     elsif (speed_now < min_speed) then
			    speeding <= UPA;
	             elsif (speed_now > internal_target) then
		            speeding <= Dn;
		     elsif (speed_now >=min_speed) and (speed_now < internal_target) then
			    speeding <= UPB;
		     end if;
		     
	   when final =>
        	if (speed_now > internal_target) then
   			    speeding <= Dn;
			elsif (speed_now >=min_speed) and (speed_now < internal_target) then
			       speeding <= UPB;
			elsif (speed_now = internal_target) then
			       speeding <= final;
			elsif (speed_now < min_speed) then
			       speeding <= UPA;
			end if;
			
	   when others =>
	   	         null;
      end case;
   end if;
end process;

phase_machine: process (reset,clk)
begin
   if reset='1' then
      cnt500 <= 499;
      cnt375 <= 374;
      cnt125 <= 124;
      pwme<='1';
      phase<=phB1;
   elsif (clk'event and clk='1') then
      case phase is
	   when phB1 =>
		case speeding is
             when UPA =>
		        cnt375<=374;
				cnt125<=124;
				cnt500<=499;
      pwme<='1';
				
		     when UPB =>
				cnt500<=499;
				cnt375<=cnt375-1;
				cnt125<=124;
      pwme<='1'; 
				
		     when Dn =>
			    cnt500<=499;
			    cnt375<=cnt375-1;
			    cnt125<=124;
      pwme<='0';
			       
		     when final =>
		        cnt500<=cnt500-1;
			    cnt375<=374;
			    cnt125<=124;
      pwme<='1';
				  
		    when others =>
		                  null;
        end case;
                
        if (cnt375=1 or cnt500=1) then
            cnt500<=499;
            cnt375<=374;  
		    phase <= phB2;
		end if;
		
	   when phB2 =>
		case speeding is
		     when UPA =>
				cnt375<=374;
				cnt125<=124;
				cnt500<=499;
      pwme<='1';
				
		     when UPB =>
				cnt500<=499;
				cnt375<=374;
				cnt125<=cnt125-1;
      pwme<='0';
				
		     when Dn =>
			    cnt500<=499;
			    cnt375<=374;
			    cnt125<=cnt125-1;
      pwme<='1';
			       
		     when final =>
		        cnt500<=cnt500-1;
			    cnt375<=374;
			    cnt125<=124;
      pwme<='0';
				  
		     when others =>
	            null;			           
		end case;
		
		if (cnt125=1 or	cnt500=1) then
                    cnt500<=499;
                    cnt125<=124;  
		    phase <= phB1;
		end if;
		
	   when others =>
	 		 null;
      end case;
   end if;
end process;

end rtl;