motfecend.c

操作系统vxworks平台下end设备的驱动程序,支持多种芯片,支持多种cpu

	{
	clDescTbl[0].clNum = clNum;
	clDescTbl[0].clSize = MOT_FEC_MAX_CL_LEN;
	}

    /* there's a cluster overhead and an alignment issue */

    clDescTbl[0].memSize = (clDescTbl[0].clNum *
			    (clDescTbl[0].clSize + CL_OVERHEAD));
    clDescTbl[0].memArea = (char *) (memalign (CL_ALIGNMENT, clSize));

    if (clDescTbl[0].memArea == NULL)
	{
	return (ERROR);
	}

    /* store the pointer to the clBlock area */

    pDrvCtrl->pClBlkArea = clDescTbl[0].memArea;
    pDrvCtrl->clBlkSize = clDescTbl[0].memSize;

    /* pool of cluster blocks */

    if (mclBlkConfig.clBlkNum == 0)
	mclBlkConfig.clBlkNum = clDescTbl[0].clNum;

    /* get memory for mblks */

    if (mclBlkConfig.memArea == NULL)
	{
	/* memory size adjusted to hold the netPool pointer at the head */

	mclBlkConfig.memSize = ((mclBlkConfig.mBlkNum
				* (M_BLK_SZ + MBLK_ALIGNMENT))
				+ (mclBlkConfig.clBlkNum
				* (CL_BLK_SZ + CL_ALIGNMENT)));

	mclBlkConfig.memArea = (char *) memalign (MBLK_ALIGNMENT,
						  mclBlkConfig.memSize);

	if (mclBlkConfig.memArea == NULL)
	    {
	    return (ERROR);
	    }

	/* store the pointer to the mBlock area */

	pDrvCtrl->pMBlkArea = mclBlkConfig.memArea;
	pDrvCtrl->mBlkSize = mclBlkConfig.memSize;
	}

    /* init the mem pool */

    if (netPoolInit (pDrvCtrl->endObj.pNetPool, &mclBlkConfig,
		     &clDescTbl[0], clDescTblNumEnt, NULL)
	== ERROR)
	{
	return (ERROR);
	}

    if ((pDrvCtrl->pClPoolId = netClPoolIdGet (pDrvCtrl->endObj.pNetPool,
					       MOT_FEC_MAX_CL_LEN, FALSE))
        == NULL)
	{
	return (ERROR);
	}

    MOT_FEC_LOG (MOT_FEC_DBG_LOAD, ("motFecInitMem... Done\n"),
				    0, 0, 0, 0, 0, 0);

    return OK;
    }

/**************************************************************************
*
* motFecStart - start the device
*
* This routine starts the FEC device and brings it up to an operational
* state.  The driver must have already been loaded with the motFecEndLoad()
* routine.
*
* RETURNS: OK, or ERROR if the device could not be initialized.
*
* INTERNAL
* The speed field inthe phyInfo structure is only set after the call
* to the physical layer init routine. On the other hand, the mib2
* interface is initialized in the motFecEndLoad() routine, and the default
* value of 10Mbit assumed there is not always correct. We need to
* correct it here.
*
*/

LOCAL STATUS motFecStart
    (
    DRV_CTRL *pDrvCtrl       /* pointer to DRV_CTRL structure */
    )
    {
    int		retVal;		/* convenient holder for return value */
    char        bucket[4];

    MOT_FEC_LOG (MOT_FEC_DBG_START, ("Starting end...\n"), 1, 2, 3, 4, 5, 6);

    /* must have been loaded */

    if (!pDrvCtrl->loaded)
	return (ERROR);

    if (vxMemProbe ((char *) (pDrvCtrl->motCpmAddr + MOT_FEC_CSR_OFF),
		    VX_READ, 4, &bucket[0]) != OK)
        {
        MOT_FEC_LOG (MOT_FEC_DBG_START,
                   (": need MMU mapping for address 0x%x\n"),
                   (UINT32) pDrvCtrl->motCpmAddr, 2, 3, 4, 5, 6);
	return (ERROR);
        }

    /* reset the chip */

    MOT_FEC_ETH_SET;
    if (motFecReset (pDrvCtrl) != OK)
	return (ERROR);

    if (motFecTbdInit (pDrvCtrl) == ERROR)
	return (ERROR);

    if (motFecRbdInit (pDrvCtrl) == ERROR)
	return (ERROR);

    /* set some flags to default values */

    pDrvCtrl->txStall = FALSE;
    pDrvCtrl->tbdIndex = 0;
    pDrvCtrl->usedTbdIndex = 0;
    pDrvCtrl->cleanTbdNum = pDrvCtrl->tbdNum;
    pDrvCtrl->rbdIndex = 0;

    /* connect the interrupt handler */

    SYS_FEC_INT_CONNECT (pDrvCtrl, motFecInt, (int) pDrvCtrl, retVal);
    if (retVal == ERROR)
	return (ERROR);

    /* enable system interrupt: set relevant bit in SIMASK */

    SYS_FEC_INT_ENABLE (pDrvCtrl, retVal);
    if (retVal == ERROR)
	return (ERROR);
	
    /* call the BSP to do any other initialization (port D) */

    SYS_FEC_ENET_ENABLE;

    /* configure some chip's registers */

    if (motFecPrePhyConfig (pDrvCtrl) == ERROR)
	return (ERROR);

    /* initialize some fields in the PHY info structure */

    if (motFecPhyPreInit (pDrvCtrl) != OK)
	{
	MOT_FEC_LOG (MOT_FEC_DBG_LOAD, ("Failed to pre-initialize the PHY\n"),
					0, 0, 0, 0, 0, 0);
	return (ERROR);
	}

    /* initialize the Physical medium layer */

    if (_func_motFecPhyInit == NULL)
	return (ERROR);

    if (((* _func_motFecPhyInit) (pDrvCtrl)) != OK)
	{
	MOT_FEC_LOG (MOT_FEC_DBG_LOAD, ("Failed to initialize the PHY\n"),
					0, 0, 0, 0, 0, 0);
	return (ERROR);
	}

    /* configure other chip's registers */

    if (motFecPostPhyConfig (pDrvCtrl) == ERROR)
	return (ERROR);

    /* correct the speed for the mib2 stuff */

    pDrvCtrl->endObj.mib2Tbl.ifSpeed = pDrvCtrl->phyInfo->phySpeed;

    if (END_FLAGS_ISSET (IFF_MULTICAST))
        MOT_FEC_FLAG_SET (MOT_FEC_MCAST);

    /* enable the Ethernet Controller */

    MOT_FEC_ETH_ENABLE;

    /* mark the interface as up */

    END_FLAGS_SET (&pDrvCtrl->endObj, (IFF_UP | IFF_RUNNING));

    /* startup the receiver */

    MOT_FEC_RX_ACTIVATE;

    /* Flush the write pipe */

    CACHE_PIPE_FLUSH ();

    MOT_FEC_LOG (MOT_FEC_DBG_START, ("Starting end... Done\n"),
				     1, 2, 3, 4, 5, 6);

    return (OK);
    }

/**************************************************************************
*
* motFecStop - stop the 'motfec' interface
*
* This routine marks the interface as inactive, disables interrupts and
* the Ethernet Controller. As a result, reception is stopped immediately,
* and transmission is stopped after a bad CRC is appended to any frame
* currently being transmitted. The reception/transmission control logic
* (FIFO pointers, buffer descriptors, etc.) is reset. To bring the
* interface back up, motFecStart() must be called.
*
* RETURNS: OK, always.
*/

LOCAL STATUS motFecStop
    (
    DRV_CTRL *  pDrvCtrl       /* pointer to DRV_CTRL structure */
    )
    {
    int		retVal;		/* convenient holder for return value */

    MOT_FEC_LOG (MOT_FEC_DBG_LOAD, ("motFecStop...\n"), 1, 2, 3, 4, 5, 6);

    /* make sure driver is operational before stopping it */

    if (END_FLAGS_GET(&pDrvCtrl->endObj) & (IFF_UP | IFF_RUNNING))
        {

        /* mark the interface as down */

        END_FLAGS_CLR (&pDrvCtrl->endObj, (IFF_UP | IFF_RUNNING));

        /* issue a graceful transmit command */

        MOT_FEC_CSR_WR (MOT_FEC_TX_CTRL_OFF, MOT_FEC_TX_CTRL_GRA);

        /* wait for the related interrupt */

        MOT_FEC_GRA_SEM_TAKE;

        /* mask chip interrupts */

        MOT_FEC_INT_DISABLE;	

        /* disable the Ethernet Controller */

        MOT_FEC_ETH_DISABLE;

        /* disable system interrupt: reset relevant bit in SIMASK */

        SYS_FEC_INT_DISABLE (pDrvCtrl, retVal);
        if (retVal == ERROR)
	    return (ERROR);

        /* disconnect the interrupt handler */

        SYS_FEC_INT_DISCONNECT (pDrvCtrl, motFecInt, (int)pDrvCtrl, retVal);
        if (retVal == ERROR)
	    return (ERROR);

        /* call the BSP to disable the Port D */

        SYS_FEC_ENET_DISABLE;

        if (motFecBdFree (pDrvCtrl) != OK)
	    return (ERROR);

        }

    MOT_FEC_LOG (MOT_FEC_DBG_LOAD, ("motFecStop... Done \n"),
				    1, 2, 3, 4, 5, 6);

    return OK;
    }

/**************************************************************************
*
* motFecReset - reset the `motFec' interface
*
* This routine resets the chip by setting the Reset bit in the Ethernet
* Control Register. The ETHER_EN bit is cleared, and all the FEC registers
* take their default values. In addition, any transmission/reception
* currently in progress is abruptly aborted.
*
* RETURNS: OK, always.
*/

LOCAL STATUS motFecReset
    (
    DRV_CTRL *  pDrvCtrl       /* pointer to DRV_CTRL structure */
    )
    {
    /* issue a reset command to the FEC chip */

    MOT_FEC_CSR_WR (MOT_FEC_CTRL_OFF, (MOT_FEC_ETH_RES | pinMux));

    /* wait at least 16 clock cycles */

    taskDelay (1);

    /* enable the FEC PIN MUX bit if necessary */

    MOT_FEC_CSR_WR (MOT_FEC_CTRL_OFF, pinMux);

    /* wait at least 16 clock cycles */

    taskDelay (1);

    return (OK);
    }

/*******************************************************************************
*
* motFecInt - entry point for handling interrupts from the FEC
*
* The interrupting events are acknowledged to the device, so that the device
* will de-assert its interrupt signal.  The amount of work done here is kept
* to a minimum; the bulk of the work is deferred to the netTask.
*
* RETURNS: N/A
*/

LOCAL void motFecInt
    (
    DRV_CTRL *  pDrvCtrl       /* pointer to DRV_CTRL structure */
    )
    {
    UINT32	event = 0;	/* event intr register */
    UINT32	mask = 0;	/* holder for the mask intr register */
    UINT32	status;		/* status word */

    CACHE_PIPE_FLUSH ();

    /* read and save the interrupt event register */

    MOT_FEC_CSR_RD (MOT_FEC_EVENT_OFF, event);

    /* clear all interrupts */

    MOT_FEC_CSR_WR (MOT_FEC_EVENT_OFF, (event & MOT_FEC_EVENT_MSK));

    CACHE_PIPE_FLUSH ();

    /* read the interrupt mask register */

    MOT_FEC_CSR_RD (MOT_FEC_MASK_OFF, mask);

    /* read CSR status word again */

    MOT_FEC_CSR_RD (MOT_FEC_EVENT_OFF, status);

    MOT_FEC_LOG (MOT_FEC_DBG_INT, ("motFecInt: event 0x%x, status 0x%x\n"),
				   (event & MOT_FEC_EVENT_MSK), status,
				   0, 0, 0, 0);

    /* handle bus error interrupts */

    if ((event & MOT_FEC_EVENT_BERR) == MOT_FEC_EVENT_BERR)
	{
	MOT_FEC_LOG (MOT_FEC_DBG_INT, ("motFecInt: bus error, restart chip\n"),
				       0, 0, 0, 0, 0, 0);

	/* stop and restart the device */

	(void) netJobAdd ((FUNCPTR) motFecStop, (int) pDrvCtrl,
			  event, 0, 0, 0);
	(void) netJobAdd ((FUNCPTR) motFecStart, (int) pDrvCtrl,
			  event, 0, 0, 0);
	}

    /* handle babbling transmit error interrupts */

    if ((event & MOT_FEC_EVENT_BABT) == MOT_FEC_EVENT_BABT)
	{