sn83932end.c

操作系统vxworks平台下end设备的驱动程序,支持多种芯片,支持多种cpu

    SnMclConfig.memSize = ((SnMclConfig.mBlkNum * (MSIZE + sizeof (long)))
                           + (SnMclConfig.clBlkNum * (CL_BLK_SZ  + 
			   sizeof (long))));

    if ((SnMclConfig.memArea = (char *) memalign (sizeof(long),
                                SnMclConfig.memSize)) == NULL)
        return (ERROR);

    /* memory requirement for cluster pools */
    SnClDescTbl[0].memSize =((SnClDescTbl[0].clNum * 
                             (OPTIMAL_CLUSTER_SIZE +8))+ sizeof(int));

    SnClDescTbl[1].memSize =((SnClDescTbl[1].clNum * (MTU_CLUSTER_SIZE +8))
                             + sizeof(int)); 

    if((SnClDescTbl[0].memArea =(char *) memalign (sizeof(long),
                                 SnClDescTbl[0].memSize))==NULL) 
        return(ERROR); 

    if((SnClDescTbl[1].memArea = (char *) memalign (sizeof(long),
                                 SnClDescTbl[1].memSize))==NULL) 
        return(ERROR); 

    if (netPoolInit(pDrvCtrl->endData.pNetPool, &SnMclConfig,
                    &SnClDescTbl[0],SnClDescTblNumEnt, NULL) == ERROR) 
        {
#ifdef DEBUG
    SN_LOGMSG("could not init buffering\n",0,0,0,0,0,0);
#endif
        return(ERROR);
        }

    /*
     * obtain the poolId for each cluster pool, needed when obtaining *
     * a cluster 
     */
    pDrvCtrl->pClPoolId[0] = clPoolIdGet(pDrvCtrl->endData.pNetPool,
                                         OPTIMAL_CLUSTER_SIZE,FALSE);

    pDrvCtrl->pClPoolId[1] = clPoolIdGet(pDrvCtrl->endData.pNetPool,
                                         MTU_CLUSTER_SIZE,FALSE);

#ifdef DEBUG
    SN_LOGMSG("init mem ok\n",0,0,0,0,0,0);
#endif
    
    return OK;
    } 


/*======================================================================*
 *	D E V I C E   C O N T R O L   R O U T I N E S	
 *======================================================================*/

/*******************************************************************************
*
* snChipReset - Place chip in Reset mode
*/

LOCAL void snChipReset
    (
    DRV_CTRL * pDrvCtrl
    )

    {
    pDrvCtrl->pDev->cr = RST;
    pDrvCtrl->pDev->rsc = 0;  /* set the sequence counter to zero */
    }


/*******************************************************************************
*
* snChipInit -  Initialize the device registers
*
* Returns: N/A
*
*/

LOCAL void snChipInit 
    (
    DRV_CTRL * pDrvCtrl
    )

    {
    SONIC * pDev;                       /* ptr to the device regs */
    u_long temp;			/* holder of physical addresses */

    pDrvCtrl->txBlocked = FALSE;
    pDev = pDrvCtrl->pDev;

    pDev->cr = RST;                     /* Turn ON RESET */
                                        /* Data Control */
    pDev->dcr = snEndDcr;
    if (snEndDcr2)
	pDev->dcr2 = snEndDcr2;
    pDev->imr = 0;                      /* All Interrupts off */
    pDev->isr = 0x7fff;                 /* Clear ISR */

    temp = (u_long) CACHE_DMA_VIRT_TO_PHYS (pDrvCtrl->RSA);
    pDev->urra = temp >> 16;            /* Upper RSA */
    pDev->rsa = temp & UMASK;           /* Lower RSA */

    temp = (u_long) CACHE_DMA_VIRT_TO_PHYS (pDrvCtrl->REA);
    pDev->rea = temp & UMASK;           /* Lower REA */

    temp = (u_long) CACHE_DMA_VIRT_TO_PHYS (pDrvCtrl->RSA);
    pDev->rrp = temp & UMASK;           /* point to first desc */
    pDev->rwp = temp & UMASK;           /* point to first desc */
    pDev->rsc = 0;

    temp = (u_long) CACHE_DMA_VIRT_TO_PHYS (pDrvCtrl->RDA);
    pDev->urda = temp >> 16;            /* Upper RDA */
    pDev->crda = temp & UMASK;          /* Lower RDA */

    temp = (u_long) CACHE_DMA_VIRT_TO_PHYS (pDrvCtrl->pTDA);
    pDev->utda = temp >> 16;            /* first TXD */
    pDev->ctda = temp & UMASK;

    pDev->cr = RST_OFF;                 /* Turn OFF RESET */
    pDev->cr = RRRA;                    /* prime with RRA read */

    pDev->rcr = BRD;			/* Accept broadcasts */
					/* Multicasts (up to 15) are 	*
					 * programmed directly into the *
					 * CAM registers.		*
					 */
    }

/*******************************************************************************
*
* snChipStart - hardware startup  of chip - sets up interupt masks and turns
*	on the receiver. 
*
* RETURNS N/A
*
*/

LOCAL void snChipStart 
    (
    DRV_CTRL * pDrvCtrl
    )

    {
    SONIC *pDev;                        /* ptr to the device regs */

    /* Point to device registers */
    pDev = pDrvCtrl->pDev;

    /* Enable transmit, receive, transmit error, & receive buffer exhaustion */
    /*SL* RDE cannot occur since there is space for 512 64 byte packets */

    /* Enable appropriate interrupts (those configured to be enabled) */
    pDev->imr = (pDrvCtrl->imr & SN_IMR_INIT);

    /* Turn on receiver */
    pDev->cr = RXEN; 

    }

/*******************************************************************************
*
* snCamMacLoad - put the local Ethernet address in the CAM
*
* First we set up a data area with the enet addr, then we tell the device
* where it is and command the device to read it.  When the device is done,
* it will interrupt us.  We wait for this interrupt with a semaphore that
* will be given by the interrupt handler.
*
* We now load all 16 CAM registers.  At initialization, all CAM descriptors
* were programmed to be broadcasts.  However, none were enabled.  In this
* routine, we program the hardware MAC address of the device unit.  The
* first CAM entry is reserved for the physical address of the unit.
* The remaining 15 are allotted to multicast addresses.  Nonewithstanding,
* whenever we load the CAM, all 16 descriptors are loaded.
*
*/

LOCAL void snCamMacLoad
    (
    DRV_CTRL * pDrvCtrl
    )

    {
     CAM_DESC * pCam;
     SONIC * pDev;


    /* Initialize pointers */
    pDev = pDrvCtrl->pDev;
    pCam = (CAM_DESC *)pDrvCtrl->CDA;


    /* Turn off load-Cam isr indication if set */
    if (pDev->isr & LCD)
	pDev->isr = LCD;


    /* Program the descriptor entry for CAM register 0 */
    pCam->cep  = 0; 
    pCam->cap0 = (pDrvCtrl->enetAddr[1] << 8) | pDrvCtrl->enetAddr[0];
    pCam->cap1 = (pDrvCtrl->enetAddr[3] << 8) | pDrvCtrl->enetAddr[2];
    pCam->cap2 = (pDrvCtrl->enetAddr[5] << 8) | pDrvCtrl->enetAddr[4];


    /* Enable the filtering for this address */
    *pDrvCtrl->pCamEnableMask |= 1;


    /* Set up Load registers */
    pDev->cdp = (u_long) CACHE_DMA_VIRT_TO_PHYS (pCam) & UMASK;
    pDev->cdc = CAM_COUNT;                         /* Number of Entries */
    pDev->cr = LCAM;                               /* issue "load CAM" cmd */


    /*
     * Wait for operation to complete since we can't do anything until
     * the MAC address is registered.  A "dead time" loop here is deemed
     * OK, since we are in initialization phase, and will only do this
     * once.
     */

    while (!(pDev->isr & LCD))
        ;

    pDev->isr = LCD;                        /* clear the event flag */

    }


/*******************************************************************************
*
* snCamMcastLoad - Load all configured Multicast addresses in the CAM
*
* This routine differs from the previous one in that only the
* entries that were set aside for multicast addresses are updated.
*
*/

LOCAL void snCamMcastLoad
    (
    DRV_CTRL * pDrvCtrl
    )
    {
    MULTI_TABLE tmpTable;
    CAM_DESC *pCam;
    SONIC *pDev;
    int num;
    int intLevel;


    pCam = (CAM_DESC *)pDrvCtrl->CDA;
    pDev = pDrvCtrl->pDev;

    /* Update our Multicast table */
    tmpTable.pTable = (char *)pDrvCtrl->mcastTable;
    tmpTable.len = sizeof (pDrvCtrl->mcastTable);
    etherMultiGet (&pDrvCtrl->endData.multiList, &tmpTable);

    /* Record the first multicast descriptor before we increment the pointer*/
    pCam++;
    pDev->cdp = (u_long) CACHE_DMA_VIRT_TO_PHYS (pCam) & UMASK;

    for (num = 1; num <= pDrvCtrl->endData.nMulti; num++, pCam++)
	{ 
    	/* Program each descriptor entry for the appropriate CAM entry */
    	pCam->cep  = num; 
    	pCam->cap0 = (tmpTable.pTable[1] << 8) | tmpTable.pTable[0];
    	pCam->cap1 = (tmpTable.pTable[3] << 8) | tmpTable.pTable[2];
    	pCam->cap2 = (tmpTable.pTable[5] << 8) | tmpTable.pTable[4];

	/* Increment to next address */
	tmpTable.pTable += 6;

        /* Enable the filtering for this address */
        *pDrvCtrl->pCamEnableMask |= (1 << num);
	}
        

    /* Set up Load registers */
    pDev->cdc = CAM_COUNT - 1;                     /* 15 MCAST entries */


    /* Make sure the TXP bit is not set in the CR, wait if it is, then load CAM    */
    intLevel = intLock();

    while (pDev->cr & TXP)
	continue;


    /* safe to issue "load CAM" cmd */
    pDev->cr = LCAM;

    intUnlock(intLevel);


    /* Make sure load command has finished before continuing */
    while (!(pDev->isr & LCD))
	continue;

    /* Turn off LCD indication */
    pDev->isr = LCD;
    }



/*============================================================================*
 * 		D R I V E R	C O N T R O L     R O U T I N E S
 *============================================================================*/

/*******************************************************************************
*
* sn83932Ioctl - the driver I/O control function
*
* Process an ioctl request.
* This is one of the routines that can be called from "outside" via
* the interface structure.
* Cannot be called before the attach, since DRV_CTRL ptr would be NULL.
*
*  Returns:  	0 - successful
*		EINVAL - invalid argument(s)
* NOMANUAL
*
*/

LOCAL int sn83932Ioctl
    (
     DRV_CTRL *pDrvCtrl,		/* ptr to device control info */
     int cmd,				/* ioctl command */
     caddr_t data			/* argument data */
    )
    {
     int value;				/* Value of data when *
					 * passed-by-value *
					 */

    /* Sanity Check */
    if (pDrvCtrl == NULL)
	return EINVAL;

    switch ((UINT)cmd)
        {
        case EIOCSADDR:
	    /* Set physical address - only valid if device is off line */
	    /* Copy address into the MIB table as well */
	    /* New address takes affect after device is started */

#ifdef DEBUG
    SN_LOGMSG ("Set Address...\n",0,0,0,0,0,0);
#endif

    	    if (data == NULL)
		return EINVAL;

	    if (pDrvCtrl->online)
		return EINVAL;

	    /* Copy the address into the device control block */
	    bcopy ((char *)data,
		   (char *)pDrvCtrl->enetAddr,
		   sizeof(pDrvCtrl->enetAddr)); 

	    /* Copy the address to the MIB table */
    	    bcopy ((char *)data,
		   (char *)pDrvCtrl->endData.mib2Tbl.ifPhysAddress.phyAddress,
		   pDrvCtrl->endData.mib2Tbl.ifPhysAddress.addrLength);

	    /* Program the new ethernet address */
	    snCamMacLoad (pDrvCtrl);
            break;


        case EIOCGADDR:
	    /* Copy address in device control area to user space */

#ifdef DEBUG
    SN_LOGMSG ("Get Address...\n",0,0,0,0,0,0);
#endif

    	    if (data == NULL)
		return EINVAL;

	    bcopy ((char *)pDrvCtrl->enetAddr,
		   (char *)data,
		   sizeof (pDrvCtrl->enetAddr));
	    break;

	case EIOCSFLAGS:
	    /* Set/Clear interface flags */

#ifdef DEBUG
    SN_LOGMSG ("Set Flags - %x...\n",(int)data,0,0,0,0,0);
#endif

	    value = (int)data;
	    if (value < 0)
		{/* Clear denoted flags */
		value = -value;
		value--;
		pDrvCtrl->endData.flags &= ~value;
		}
	    else
		/* Set flags */
		pDrvCtrl->endData.flags |= value;

	    snIfConfig (pDrvCtrl, value);
	    break;

	case EIOCGFLAGS:
	    /* Get interface flags */

#ifdef DEBUG
    SN_LOGMSG ("Get Flags...\n",0,0,0,0,0,0);
#endif

    	    if (data == NULL)
		return EINVAL;

	    *(int *)data = END_FLAGS_GET (&pDrvCtrl->endData);
	    break;

	case EIOCPOLLSTART:
	    /* Put device in poll mode */

	    snPollStart (pDrvCtrl);
	    break;

	case EIOCPOLLSTOP:
	    /* Put device into interrupt mode */

	    snPollStop (pDrvCtrl);
	    break;

/*SL*/	case EIOCGMIB2:
	    /* Get the MIB2 table */

#ifdef DEBUG
    SN_LOGMSG ("Get MIBS...\n",0,0,0,0,0,0);
#endif

    	    if (data == NULL)
		return EINVAL;

	    bcopy ((char *)&pDrvCtrl->endData.mib2Tbl, (char *)data,
		   sizeof (pDrvCtrl->endData.mib2Tbl));
	    break;

	case EIOCGFBUF:
	    /* Get some minimum buf size of first buffer in scatter xmit */
	    
#ifdef DEBUG
    SN_LOGMSG ("Get MIN_BUF_SIZE...\n",0,0,0,0,0,0);
#endif