bcm1250macend.c

操作系统vxworks平台下end设备的驱动程序,支持多种芯片,支持多种cpu

    while ((status = ETH_MAC_REG_READ (pDrvCtrl->regIsr)) != 0)
        {
        DRV_LOG (DRV_DEBUG_INT, "status = 0x%x\n", status, 2, 3, 4, 5, 6);

        /* Check for receive channel 0 interrupt */

        if ((!pDrvCtrl->rxDma.hndlAct) &&
            (status & (M_MAC_INT_CHANNEL << S_MAC_RX_CH0)))
            {
            pDrvCtrl->rxDma.hndlAct = TRUE;
            (void)netJobAdd ((FUNCPTR)bcm1250MacRxHandle, (int)pDrvCtrl, 0,
                              0, 0, 0);
            }

        /* Check for transmit channel 0 interrupt */

        if ((!pDrvCtrl->txDma.hndlAct) &&
            (status & (M_MAC_INT_CHANNEL << S_MAC_TX_CH0)))
            {
            pDrvCtrl->txDma.hndlAct = TRUE;
            (void)netJobAdd ((FUNCPTR)bcm1250MacTxHandle, (int)pDrvCtrl, 0,
                              0, 0, 0);
            }
        }
    }


/*******************************************************************************
*
* bcm1250MacRxHandle - task-level routine to service receive frame interrupts
*
* This routine processes received frame interrupts, and runs at task level
* context in the netTask task.  Ethernet frames are received at the headIndex,
* and ethernet DMA hardware is given DMA buffer descriptors to receive into
* with the tailIndex.
*
* RETURNS: N/A
*/

LOCAL void bcm1250MacRxHandle
    (
    DRV_CTRL *  pDrvCtrl    /* driver control structure */
    )
    {
    ETH_MAC_DMA *   pRxDma;     /* ethernet DMA structure */
    ETH_DMA_DSCR *  pRxDscr;    /* DMA buffer descriptor */
    ETH_DMA_DSCR *  pCurrDscr;  /* points to current buffer descriptor */
    M_BLK_ID        pMblk;      /* mBlk pointer */
    CL_BLK_ID       pClBlk;     /* cBlk pointer */
    char *          pBuf;       /* cluster pointer */
    char *          pData;      /* received frame data pointer */
    int             len;        /* frame length */

    DRV_LOG (DRV_DEBUG_RX, "bcm1250MacRxHandle ......\n", 1, 2, 3, 4, 5, 6);

    pRxDma = &pDrvCtrl->rxDma;

    while (TRUE)
        {
        /* Point to next descriptor to be filled by the receiver. */

        pCurrDscr = (ETH_DMA_DSCR *)((UINT32)(ETH_DMA_REG_READ(
                                                 pRxDma->regCurDscr) &
                                              M_DMA_CURDSCR_ADDR));

        /* Point to next descriptor to be processed by this routine. */

        pRxDscr = &pRxDma->pDscrTable[pRxDma->headIndex];

        /* 
         * If all the full descriptors been processed, 
         * then break out of the loop and exit. 
         */

        if ((UINT32)pCurrDscr == KVTOPHYS (pRxDscr))
            {
            DRV_LOG (DRV_DEBUG_RX, "pRxDscr:0x%x catch pCurrPtr:0x%x\n",
                     (int)pRxDscr, (int)pCurrDscr, 3, 4, 5, 6);
            break;
            }

        /* Get pointer to received frame */

        pData = (char *)PHYSTOV ((UINT32)(pRxDscr->dscr_a));

        /* Check this received frame for an error. */

        if (pRxDscr->dscr_a & M_DMA_ETHRX_BAD)
            {
            DRV_LOG (DRV_DEBUG_RX, "bad frame\n", 1, 2, 3, 4, 5, 6);
            END_ERR_ADD (&pDrvCtrl->endObj, MIB2_IN_ERRS, 1);

            /* Point to next descriptor to be given to the hardware */

            pRxDscr = &pRxDma->pDscrTable[pRxDma->tailIndex];

            pRxDscr->dscr_a = KVTOPHYS ((UINT32)pData) |
                              V_DMA_DSCRA_A_SIZE (MAX_FRAME_CACHE_BLKS) |
                              M_DMA_DSCRA_INTERRUPT;
            pRxDscr->dscr_b = 0;

            /* mark the descriptor ready to receive */

            ETH_DMA_REG_WRITE (pRxDma->regDscrCnt, 1);

            /* advance ring management variables */

            pRxDma->tailIndex = (pRxDma->tailIndex + 1) % pRxDma->maxDescr;
            pRxDma->headIndex = (pRxDma->headIndex + 1) % pRxDma->maxDescr;
            continue;   /* back to top of while loop */
            }

        /* Process good frame received. */

        DRV_LOG (DRV_DEBUG_RX, "good frame\n", 1, 2, 3, 4, 5, 6);

        /* Update MIB-II variables */

        END_ERR_ADD (&pDrvCtrl->endObj, MIB2_IN_UCAST, 1);

        len = (int)G_DMA_DSCRB_PKT_SIZE (pRxDscr->dscr_b) - 4;

        pBuf = pData;
        DRV_LOG (DRV_DEBUG_RXD, "rx - pData= 0x%08x, len=%d\n", (int)pBuf,
                 len, 3, 4, 5, 6);
        DRV_LOG (DRV_DEBUG_RXD,
                 "rx - *pBuf= 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x\n",
                 pBuf[0], pBuf[1], pBuf[2], pBuf[3], pBuf[4], pBuf[5]);
        DRV_LOG (DRV_DEBUG_RXD,
                 "rx - *pBuf= 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x\n",
                 pBuf[6], pBuf[7], pBuf[8], pBuf[9], pBuf[10], pBuf[11]);
        DRV_LOG (DRV_DEBUG_RXD,
                 "rx - *pBuf= 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x\n",
                 pBuf[12], pBuf[13], pBuf[14], pBuf[15], pBuf[16], pBuf[17]);

        /* Allocate mBlk/clBlk/Cluster */

        pMblk = NET_MBLK_ALLOC ();
        pClBlk = NET_CL_BLK_ALLOC ();
        pBuf = NET_BUF_ALLOC ();

        /* If an allocation failed, discard the frame. */

        if ((pMblk == (M_BLK *)NULL) ||
            (pBuf == (char *)NULL) ||
            (pClBlk == (CL_BLK *)NULL))
            {
            DRV_LOG (DRV_DEBUG_RX, "not available RxBufs\n",
                     1, 2, 3, 4, 5, 6);
            END_ERR_ADD (&pDrvCtrl->endObj, MIB2_IN_ERRS, 1);
            pDrvCtrl->lastError.errCode = END_ERR_NO_BUF;
            muxError(&pDrvCtrl->endObj, &pDrvCtrl->lastError);

            /* Free any allocations that succeeded. */

            if (pMblk != (M_BLK *)NULL)
                NET_MBLK_FREE (pMblk);
            if (pBuf != (char *)NULL)
                NET_BUF_FREE (pBuf);
            if (pClBlk != (CL_BLK *)NULL)
                NET_CL_BLK_FREE (pClBlk);

            /* Point to next descriptor to be given to the hardware */

            pRxDscr = &pRxDma->pDscrTable[pRxDma->tailIndex];

            /* Re-arm this descriptor with the same buffer. */

            pRxDscr->dscr_a = KVTOPHYS ((UINT32)pData) |
                              V_DMA_DSCRA_A_SIZE (MAX_FRAME_CACHE_BLKS) |
                              M_DMA_DSCRA_INTERRUPT;
            pRxDscr->dscr_b = 0;

            /* mark the descriptor ready to receive */

            ETH_DMA_REG_WRITE (pRxDma->regDscrCnt, 1);

            /* advance ring management variables */

            pRxDma->tailIndex = (pRxDma->tailIndex + 1) % pRxDma->maxDescr;
            pRxDma->headIndex = (pRxDma->headIndex + 1) % pRxDma->maxDescr;
            continue;   /* back to top of while loop */
            }

        /* Point to next descriptor to be given to the hardware */

        pRxDscr = &pRxDma->pDscrTable[pRxDma->tailIndex];

        /* Re-arm this descriptor with the new buffer. */

        pRxDscr->dscr_a = KVTOPHYS ((UINT32)pBuf) |
                          V_DMA_DSCRA_A_SIZE (MAX_FRAME_CACHE_BLKS) |
                          M_DMA_DSCRA_INTERRUPT | VXW_RCV_BUF_OFFSET;
        pRxDscr->dscr_b = 0;

        /* mark the descriptor ready to receive */

        ETH_DMA_REG_WRITE (pRxDma->regDscrCnt, 1);

        /* send the frame to the upper layer */

        NET_CL_BLK_JOIN (pClBlk, pData - VXW_RCV_BUF_OFFSET,
                         MAX_FRAME_SIZE);
        NET_MBLK_CL_JOIN (pMblk, pClBlk);

        pMblk->mBlkHdr.mFlags |= M_PKTHDR;
        pMblk->mBlkHdr.mData = pData;
        pMblk->mBlkHdr.mLen = len;
        pMblk->mBlkPktHdr.len = pMblk->mBlkHdr.mLen;

        END_RCV_RTN_CALL (&pDrvCtrl->endObj, pMblk);

        DRV_LOG (DRV_DEBUG_RXD,
                 "rx - pMblk=0x%08x pClBlk=0x%08x pBuf=0x%08x\n",
                 (int)pMblk, (int)pClBlk, (int)pBuf, 4, 5, 6);

        /* advance ring management variables */

        pRxDma->tailIndex = (pRxDma->tailIndex + 1) % pRxDma->maxDescr;
        pRxDma->headIndex = (pRxDma->headIndex + 1) % pRxDma->maxDescr;
        }

    DRV_LOG (DRV_DEBUG_RX, "bcm1250MacRxHandle Done.\n", 1, 2, 3, 4, 5, 6);
    pRxDma->hndlAct = FALSE;
    }


/*******************************************************************************
*
* bcm1250MacTxHandle - task-level routine to service transmit frame interrupts
*
* This routine is processes transmit frame interrupts, and runs at task level
* context in the netTask task.
*
* RETURNS: N/A
*/

LOCAL void bcm1250MacTxHandle
    (
    DRV_CTRL *  pDrvCtrl    /* driver control structure */
    )
    {
    ETH_MAC_DMA *   pTxDma;             /* ethernet DMA structure */
    ETH_DMA_DSCR *  pTxDscr;            /* DMA buffer descriptor */
    ETH_DMA_DSCR *  pCurrDscr;          /* points to current descriptor */
    TX_BUF_TABLE *  pBufTbl;            /* points to current buffer table */
    BOOL            restart = FALSE;    /* mux restart flag */

    DRV_LOG (DRV_DEBUG_TX, "bcm1250MacTxHandle ......\n", 1, 2, 3, 4, 5, 6);

    pTxDma = &(pDrvCtrl->txDma);

    while (TRUE)
        {
        /* Point to next descriptor to be transmitted by the hardware. */

        pCurrDscr = (ETH_DMA_DSCR *)((UINT32)(ETH_DMA_REG_READ (
                                                 pTxDma->regCurDscr) &
                                              M_DMA_CURDSCR_ADDR));

        /* Point to next descriptor to be processed by this routine. */

        pTxDscr = &pTxDma->pDscrTable[pTxDma->headIndex];

        /* Have all the transmit complete descriptors been processed? */

        if ((UINT32)pCurrDscr == KVTOPHYS (pTxDscr))
             break;

        DRV_LOG (DRV_DEBUG_TX, "tx_remindex=0x%x, curdscr=0x%x, remdscr=0x%x\n",
                 pTxDma->headIndex, (int)pCurrDscr, (int)pTxDscr, 4, 5, 6);

        /* point to current descriptors buffer table entry. */

        pBufTbl = &pTxDma->bufTable[pTxDma->headIndex];

        /* free this descriptors buffer */

        if (pBufTbl->pBuf != (char *)NULL)
            {
            if (pBufTbl->type == BUF_TYPE_CL)
                {
                NET_BUF_FREE (pBufTbl->pBuf);
                }
            else if (pBufTbl->type == BUF_TYPE_MBLK)
                {
                netMblkClChainFree ((M_BLK *)pBufTbl->pBuf);
                }
            else
                {
                DRV_LOG (DRV_DEBUG_TX,
                         "unknown buffer type when try to release tx buf\n",
                         1, 2, 3, 4, 5, 6);
                }
            pBufTbl->pBuf = (char *)NULL;
            pBufTbl->type = BUF_TYPE_NONE;
            }

        /* Update descriptor index and count variables */

        END_TX_SEM_TAKE (&pDrvCtrl->endObj, WAIT_FOREVER);
        pTxDma->headIndex = (pTxDma->headIndex + 1) % pTxDma->maxDescr;
        pTxDma->ringCount--;
        END_TX_SEM_GIVE (&pDrvCtrl->endObj);

        /* Indicate that we need to check for the restart condition. */

        restart = TRUE;
        }

    /*
     * Does the Mux need to be restarted, and do we have plenty of DMA buffer
     * descriptors?
     */

    if ((restart) && (pTxDma->txBlocked) && (pTxDma->ringCount < 5))
        {
            pTxDma->txBlocked = FALSE;
            muxTxRestart ((void *)&pDrvCtrl->endObj);
        }

    DRV_LOG (DRV_DEBUG_TX, "bcm1250MacTxHandle Done.\n", 1, 2, 3, 4, 5, 6);

    /* Indicate that all transmit descriptors have been processed. */

    pTxDma->hndlAct = FALSE;
    }


/*******************************************************************************
* bcm1250MacPollSend - routine to send a packet in polled mode.
*
* This routine is called by a user to try and send a packet on the
* device.
*
* RETURNS: OK upon success.  EAGAIN if device is busy.
*/

LOCAL STATUS bcm1250MacPollSend
    (
    DRV_CTRL *  pDrvCtrl,   /* driver control structure */
    M_BLK *     pMblk       /* mBlk to transmit */
    )
    {
    ETH_MAC_DMA *   pTxDma;     /* ethernet DMA structure */
    ETH_DMA_DSCR *  pTxDscr;    /* DMA buffer descriptor */
    ETH_DMA_DSCR *  pCurrDscr;  /* current descriptor */
    TX_BUF_TABLE *  pBufTbl;            /* points to current buffer table */
    int             len;        /* length of frame */

    DRV_LOG (DRV_DEBUG_TX, "bcm1250MacPollSend enter ......\n",
              1, 2, 3, 4, 5, 6);

    pTxDma = &pDrvCtrl->txDma;

    /* DMA buffer descriptors available? */

    if (pTxDma->ringCount >= pTxDma->maxDescr)
        {
        DRV_LOG (DRV_DEBUG_TX, "No available TxBufs\n", 1, 2, 3, 4, 5, 6);
        END_ERR_ADD (&pDrvCtrl->endObj, MIB2_OUT_ERRS, 1);

        return (EAGAIN); /* just return without freeing mBlk chain */
        }

    len = netMblkToBufCopy (pMblk, pTxPollBuf, (FUNCPTR)NULL);
    len = max (ETHERSMALL, len);

    DRV_LOG (DRV_DEBUG_TXD,
             "tx - *pTxPollBuf= 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x\n",
             pTxPollBuf[0], pTxPollBuf[1], pTxPollBuf[2], pTxPollBuf[3], pTxPollBuf[4], pTxPollBuf[5]);
    DRV_LOG (DRV_DEBUG_TXD,
             "tx - *pTxPollBuf= 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x\n",
             pTxPollBuf[6], pTxPollBuf[7], pTxPollBuf[8], pTxPollBuf[9], pTxPollBuf[10], pTxPollBuf[11]);
    DRV_LOG (DRV_DEBUG_TXD,
             "tx - *pTxPollBuf= 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x\n",
             pTxPollBuf[12], pTxPollBuf[13], pTxPollBuf[14], pTxPollBuf[15], pTxPollBuf[16], pTxPollBuf[17]);

    pTxDscr = &pTxDma->pDscrTable[pTxDma->tailIndex];

    /* set txbuf ptr, cache line size, ...  */

    pTxDscr->dscr_a = (UINT64)((UINT32)KVTOPHYS (pTxPollBuf)) |
                      V_DMA_DSCRA_A_SIZE (NUMCACHEBLKS (len)) |
                      M_DMA_ETHTX_SOP;

    /* set pkt len and option */

    pTxDscr->dscr_b = V_DMA_DSCRB_OPTIONS (K_DMA_ETHTX_APPENDCRC_APPENDPAD) |
                      V_DMA_DSCRB_PKT_SIZE (len);

    /* save the buf info */

    pTxDma->bufTable[pTxDma->tailIndex].pBuf = pTxPollBuf;
    pTxDma->bufTable[pTxDma->tailIndex].type = BUF_TYPE_CL;

    /* Advance ring management variables */

    pTxDma->tailIndex = (pTxDma->tailIndex + 1) % pTxDma->maxDescr;
    pTxDma->ringCount++;

    ETH_DMA_REG_WRITE (pTxDma->regDscrCnt, 1);

    while (TRUE)