adc10.h

Microchip的官方PIC24H系列16位单片机的外设源程序库。

/********************************************************************/
/*              Header for 10bit ADC module library functions       */
/*******************************************************************/
#if defined(__dsPIC30F2010__) || defined(__dsPIC30F3010__) || defined(__dsPIC30F4012__) || defined(__dsPIC30F3011__) \
    || defined(__dsPIC30F4011__) || defined(__dsPIC30F5015__) || defined(__dsPIC30F6010__)
#ifndef __ADC10_H
#define __ADC10_H

/* List of SFRs for ADC */
/* This list contains the SFRs with default (POR) values to be used for configuring ADC */
/* The user can modify this based on the requirement */
#define ADCON1_VALUE               0x0000
#define ADCON2_VALUE               0x0000
#define ADCON3_VALUE               0x0000
#define ADCHS_VALUE                0x0000
#define ADPCFG_VALUE               0x0000
#define ADCSSL_VALUE               0x0000

/* ADCON1 Configuration Bit Definitions */

#define ADC_MODULE_ON               0xFFFF /* A/D Converter on */
#define ADC_MODULE_OFF              0x7FFF /* A/D Converter off */

#define ADC_IDLE_CONTINUE           0xDFFF /* A/D Operate in Idle mode */
#define ADC_IDLE_STOP               0xFFFF /* A/D Stop in Idle mode */

#define ADC_FORMAT_SIGN_FRACT       0xFFFF /* A/D data format signed fractional */
#define ADC_FORMAT_FRACT            0xFEFF /* A/D data format fractional */
#define ADC_FORMAT_SIGN_INT         0xFDFF /* A/D data format signed integer */
#define ADC_FORMAT_INTG             0xFCFF /* A/D data format integer */

/* SSRC<2:0> bit defines */
/* Internal counter ends sampling and starts conversion (Auto convert) */
#define ADC_CLK_AUTO                0xFFFF

/* MPWM interval ends sampling and starts conversion */
#define ADC_CLK_MPWM                0xFF7F

/* Timer compare ends sampling and starts conversion */
#define ADC_CLK_TMR                 0xFF5F

/* Active transition on INT0 ends sampling and starts conversion */
#define ADC_CLK_INT0                0xFF3F

/* Clearing sample (SAMP) bit ends sampling and starts conversion */
#define ADC_CLK_MANUAL              0xFF1F

/* Simultaneous sampling bits */
#define ADC_SAMPLE_SIMULTANEOUS     0xFFFF
#define ADC_SAMPLE_INDIVIDUAL       0xFFF7

/* Auto sampling Select */
#define ADC_AUTO_SAMPLING_ON        0xFFFF

/* Samples multiple channels individually in sequence */
#define ADC_AUTO_SAMPLING_OFF       0xFFFB

/* sample / hold amplifiers are sampling */
#define ADC_SAMP_ON                 0xFFFF
/* sample / hold amplifiers are holding */
#define ADC_SAMP_OFF                0xFFFD
#define ADC_SAMP_OFF                0xFFFD

/* defines for the ADCON2 register */

/* A/D Voltage reference configuration Vref+ is AVdd and Vref- is AVss */
#define ADC_VREF_AVDD_AVSS          0x0FFF
/* A/D Voltage reference configuration Vref+ external and Vref- is AVss */
#define ADC_VREF_EXT_AVSS           0x2FFF
/* A/D Voltage reference configuration Vref+ AVdd and Vref- external */
#define ADC_VREF_AVDD_EXT           0x4FFF
/* A/D Voltage reference configuration both Vref+ and Vref- are external */
#define ADC_VREF_EXT_EXT            0x6FFF

/* A/D Scan Input Selections for CH0 during SAMPLE A */
#define ADC_SCAN_ON                 0xEFFF
/* A/D Do notScan Input Selections for CH0+ during SAMPLE A */
#define ADC_SCAN_OFF                0xEBFF

/* A/D channels utilised */
#define ADC_CONVERT_CH_0ABC         0xEFFF
#define ADC_CONVERT_CH_0A           0xEDFF
#define ADC_CONVERT_CH0             0xECFF

/* A/D Interrupt at the completion of conversion for each sample */
#define ADC_SAMPLES_PER_INT_1       0xEFC3
/* A/D Interrupt at the completion of conversion for each 2nd sample */
#define ADC_SAMPLES_PER_INT_2       0xEFC7
/* A/D interrupt at the completion of conversion for each 3rd sample */
#define ADC_SAMPLES_PER_INT_3       0xEFCB
/* A/D interrupt at the completion of conversion for each 4th sample */
#define ADC_SAMPLES_PER_INT_4       0xEFCF
/* A/D interrupt at the completion of conversion for each 5th sample */
#define ADC_SAMPLES_PER_INT_5       0xEFD3
/* A/D interrupt at the completion of conversion for each 6th sample */
#define ADC_SAMPLES_PER_INT_6       0xEFD7
/* A/D interrupt at the completion of conversion for each 7th sample */
#define ADC_SAMPLES_PER_INT_7       0xEFDB
/* A/D interrupt at the completion of conversion for each 8th sample */
#define ADC_SAMPLES_PER_INT_8       0xEFDF
/* A/D interrupt at the completion of conversion for each 9th sample */
#define ADC_SAMPLES_PER_INT_9       0xEFE3
/* A/D interrupt at the completion of conversion for each 10th sample */
#define ADC_SAMPLES_PER_INT_10      0xEFE7
/* A/D interrupt at the completion of conversion for each 11th sample */
#define ADC_SAMPLES_PER_INT_11      0xEFEB
/* A/D interrupt at the completion of conversion for each 12th sample */
#define ADC_SAMPLES_PER_INT_12      0xEFEF
/* A/D interrupt at the completion of conversion for each 13th sample */
#define ADC_SAMPLES_PER_INT_13      0xEFF3
/* A/D interrupt at the completion of conversion for each 14th sample */
#define ADC_SAMPLES_PER_INT_14      0xEFF7
/* A/D interrupt at the completion of conversion for each 15th sample */
#define ADC_SAMPLES_PER_INT_15      0xEFFB
/* A/D interrupt at the completion of conversion for each 16th sample */
#define ADC_SAMPLES_PER_INT_16      0xEFFF

/* BUFM bit defines */
#define ADC_ALT_BUF_ON              0xEFFF /* Buffer configured as 2 8-word buffers */
#define ADC_ALT_BUF_OFF             0xEFFD /* Buffer configured as 1 16-word buffer */

/* A/D Uses channel input selects for SAMPLE A on first sample and SAMPLE B on next sample */
#define ADC_ALT_INPUT_ON            0xEFFF /* alternate between MUXA and MUXB */

/* A/D Always uses channel input selects for SAMPLE A */
#define ADC_ALT_INPUT_OFF           0xEFFE /* use MUXA only */

/* defines for ADCON3 register */
#define ADC_SAMPLE_TIME_0           0xE0FF /* A/D Auto Sample Time 0 Tad */
#define ADC_SAMPLE_TIME_1           0xE1FF /* A/D Auto Sample Time 1 Tad */
#define ADC_SAMPLE_TIME_2           0xE2FF /* A/D Auto Sample Time 2 Tad */
#define ADC_SAMPLE_TIME_3           0xE3FF /* A/D Auto Sample Time 3 Tad */
#define ADC_SAMPLE_TIME_4           0xE4FF /* A/D Auto Sample Time 4 Tad */
#define ADC_SAMPLE_TIME_5           0xE5FF /* A/D Auto Sample Time 5 Tad */
#define ADC_SAMPLE_TIME_6           0xE6FF /* A/D Auto Sample Time 6 Tad */
#define ADC_SAMPLE_TIME_7           0xE7FF /* A/D Auto Sample Time 7 Tad */
#define ADC_SAMPLE_TIME_8           0xE8FF /* A/D Auto Sample Time 8 Tad */
#define ADC_SAMPLE_TIME_9           0xE9FF /* A/D Auto Sample Time 9 Tad */
#define ADC_SAMPLE_TIME_10          0xEAFF /* A/D Auto Sample Time 10 Tad */
#define ADC_SAMPLE_TIME_11          0xEBFF /* A/D Auto Sample Time 11 Tad */
#define ADC_SAMPLE_TIME_12          0xECFF /* A/D Auto Sample Time 12 Tad */
#define ADC_SAMPLE_TIME_13          0xEDFF /* A/D Auto Sample Time 13 Tad */
#define ADC_SAMPLE_TIME_14          0xEEFF /* A/D Auto Sample Time 14 Tad */
#define ADC_SAMPLE_TIME_15          0xEFFF /* A/D Auto Sample Time 15 Tad */
#define ADC_SAMPLE_TIME_16          0xF0FF /* A/D Auto Sample Time 16 Tad */
#define ADC_SAMPLE_TIME_17          0xF1FF /* A/D Auto Sample Time 17 Tad */
#define ADC_SAMPLE_TIME_18          0xF2FF /* A/D Auto Sample Time 18 Tad */
#define ADC_SAMPLE_TIME_19          0xF3FF /* A/D Auto Sample Time 19 Tad */
#define ADC_SAMPLE_TIME_20          0xF4FF /* A/D Auto Sample Time 20 Tad */
#define ADC_SAMPLE_TIME_21          0xF5FF /* A/D Auto Sample Time 21 Tad */
#define ADC_SAMPLE_TIME_22          0xF6FF /* A/D Auto Sample Time 22 Tad */
#define ADC_SAMPLE_TIME_23          0xF7FF /* A/D Auto Sample Time 23 Tad */
#define ADC_SAMPLE_TIME_24          0xF8FF /* A/D Auto Sample Time 24 Tad */
#define ADC_SAMPLE_TIME_25          0xF9FF /* A/D Auto Sample Time 25 Tad */
#define ADC_SAMPLE_TIME_26          0xFAFF /* A/D Auto Sample Time 26 Tad */
#define ADC_SAMPLE_TIME_27          0xFBFF /* A/D Auto Sample Time 27 Tad */
#define ADC_SAMPLE_TIME_28          0xFCFF /* A/D Auto Sample Time 28 Tad */
#define ADC_SAMPLE_TIME_29          0xFDFF /* A/D Auto Sample Time 29 Tad */
#define ADC_SAMPLE_TIME_30          0xFEFF /* A/D Auto Sample Time 30 Tad */
#define ADC_SAMPLE_TIME_31          0xFFFF /* A/D Auto Sample Time 31 Tad */

/* A/D Conversion Clock Source internal RC Clock */
#define ADC_CONV_CLK_INTERNAL_RC    0xFFFF
/* A/D Conversion Clock Source Clock derived from system clock */
#define ADC_CONV_CLK_SYSTEM         0xFF7F

/* A/D conversion clock select bit ADCS<5:0>*/
#define ADC_CONV_CLK_32Tcy          0xFFFF  /* A/D Conversion Clock Select bits */
#define ADC_CONV_CLK_63Tcy2         0xFFFE  /* A/D Conversion Clock Select bits */
#define ADC_CONV_CLK_31Tcy          0xFFFD  /* A/D Conversion Clock Select bits */
#define ADC_CONV_CLK_61Tcy2         0xFFFC  /* A/D Conversion Clock Select bits */
#define ADC_CONV_CLK_30Tcy          0xFFFB
#define ADC_CONV_CLK_59Tcy2         0xFFFA
#define ADC_CONV_CLK_29Tcy          0xFFF9
#define ADC_CONV_CLK_57Tcy2         0xFFF8
#define ADC_CONV_CLK_28Tcy          0xFFF7
#define ADC_CONV_CLK_55Tcy2         0xFFF6
#define ADC_CONV_CLK_27Tcy          0xFFF5
#define ADC_CONV_CLK_53Tcy2         0xFFF4
#define ADC_CONV_CLK_26Tcy          0xFFF3
#define ADC_CONV_CLK_51Tcy2         0xFFF2
#define ADC_CONV_CLK_25Tcy          0xFFF1
#define ADC_CONV_CLK_49Tcy2         0xFFF0
#define ADC_CONV_CLK_24Tcy          0xFFEF
#define ADC_CONV_CLK_47Tcy2         0xFFEE
#define ADC_CONV_CLK_23Tcy          0xFFED
#define ADC_CONV_CLK_45Tcy2         0xFFEC
#define ADC_CONV_CLK_22Tcy          0xFFEB
#define ADC_CONV_CLK_43Tcy2         0xFFEA
#define ADC_CONV_CLK_21Tcy          0xFFE9
#define ADC_CONV_CLK_41Tcy2         0xFFE8
#define ADC_CONV_CLK_20Tcy          0xFFE7
#define ADC_CONV_CLK_39Tcy2         0xFFE6
#define ADC_CONV_CLK_19Tcy          0xFFE5
#define ADC_CONV_CLK_37Tcy2         0xFFE4
#define ADC_CONV_CLK_18Tcy          0xFFE3