init.c

DSP 6711 SPI主模式下与MCU通信程序

//#include <stdio.h>
#include <csl_pll.h>
#include <csl_cache.h>
#include <csl_mcbsp.h>



void PLLinit()
{
	PLL_Config pllcfg;
	Uint32 osc_cdtion,oscratio;
	//PLL_Init pll_i={6,1,1,3,3,8};
	//PLL_init(&pll_i);
	//CSL_init();	
	osc_cdtion=PLL_clkTest();	//Checks the oscillator input stable condition
	PLL_getConfig(&pllcfg);	//Reads the current PLL controller configuration values
	
	PLL_bypass();	//	1)Sets the PLL in bypass mode
	PLL_reset();	//	2)Resets the PLL
/*	oscratio=PLL_getOscRatio();
	PLL_setOscRatio(9);
	oscratio=PLL_getOscRatio();
*/

//	PLL_getConfig(&pllcfg);
	PLL_setMultiplier(0x06);		//Sets the PLL multiplier value:*6
	//PLL_setPllRatio(PLL_DIV2,5);	//Sets the PLL divide ratio: div2:/6
	//PLL_setPllRatio(PLL_DIV0,0);
	//PLL_setPllRatio(PLL_DIV1,1);
	//PLL_setPllRatio(PLL_DIV3,4);
	//PLL_init(&pll_i);
	//PLL_configArgs(0x0048,0x0007,0x8000,0x8000,0x80002,0x8001,0x8007);

	PLL_deassert();
	PLL_enable();
//	PLL_getConfig(&pllcfg);
}


void L2cacheinit()
{
//	Uint32 L2sramsize;	
	CACHE_L2Mode L2mode;
//	L2sramsize=CACHE_getL2SramSize();	//spru401i	P77

	L2mode=CACHE_setL2Mode(CACHE_48KSRAM);	//spru401i P84
//	L2sramsize=CACHE_getL2SramSize();
	
}

void MCBSP1init()
{
	extern MCBSP_Handle hMcbsp1;
	extern MCBSP_Config mcbspCfg1;
	Uint32 clkstpval;

	MCBSP_Config mcbspCfg = {
		MCBSP_SPCR_RMK(  
           MCBSP_SPCR_FREE_DEFAULT,
           MCBSP_SPCR_SOFT_DEFAULT,
           MCBSP_SPCR_FRST_DEFAULT,
           MCBSP_SPCR_GRST_DEFAULT,
           MCBSP_SPCR_XINTM_DEFAULT,
           MCBSP_SPCR_XSYNCERR_DEFAULT,
           MCBSP_SPCR_XRST_DEFAULT,
           MCBSP_SPCR_DLB_DEFAULT,
           MCBSP_SPCR_RJUST_DEFAULT,
           MCBSP_SPCR_CLKSTP_NODELAY, /* CLKSTP=10b with CLKXP=0, clock starts with */
           MCBSP_SPCR_DXENA_OFF,    /* rising edge without delay                     */
           MCBSP_SPCR_RINTM_DEFAULT,
           MCBSP_SPCR_RSYNCERR_DEFAULT,
           MCBSP_SPCR_RRST_DEFAULT
           ),
	    MCBSP_RCR_RMK(
           MCBSP_RCR_RPHASE_SINGLE,
           MCBSP_RCR_RFRLEN2_DEFAULT,
           MCBSP_RCR_RWDLEN2_DEFAULT,
           MCBSP_RCR_RCOMPAND_DEFAULT,
           MCBSP_RCR_RFIG_NO,
           MCBSP_RCR_RDATDLY_1BIT,   /* 1 bit data delay */
           MCBSP_RCR_RFRLEN1_DEFAULT,
           MCBSP_RCR_RWDLEN1_8BIT,  /* receive element length phase 1 is 8 bits */
           MCBSP_RCR_RWDREVRS_DISABLE
           ),
	    MCBSP_XCR_RMK(
           MCBSP_XCR_XPHASE_DEFAULT,
           MCBSP_XCR_XFRLEN2_DEFAULT,
           MCBSP_XCR_XWDLEN2_DEFAULT,
           MCBSP_XCR_XCOMPAND_DEFAULT,
           MCBSP_XCR_XFIG_DEFAULT,
           MCBSP_XCR_XDATDLY_1BIT,    /* 1 bit data delay                    */
           MCBSP_XCR_XFRLEN1_DEFAULT,
           MCBSP_XCR_XWDLEN1_8BIT,   /* transmit element phase 1 is 8 bits */
           MCBSP_XCR_XWDREVRS_DISABLE
           ),
		MCBSP_SRGR_RMK(
           MCBSP_SRGR_GSYNC_FREE,
           MCBSP_SRGR_CLKSP_RISING,
           MCBSP_SRGR_CLKSM_INTERNAL, /* SRGR clock mode from internal source */
           MCBSP_SRGR_FSGM_DEFAULT,
           MCBSP_SRGR_FPER_DEFAULT,
           MCBSP_SRGR_FWID_DEFAULT,
           MCBSP_SRGR_CLKGDV_OF(0x5f) /* divide clock by factor of 95         */
           ),
	    MCBSP_MCR_RMK(
           MCBSP_MCR_XPBBLK_DEFAULT, /* All fields in MCR set to default values    */
           MCBSP_MCR_XPABLK_DEFAULT,
           MCBSP_MCR_XMCM_DEFAULT,
           MCBSP_MCR_RPBBLK_DEFAULT,
           MCBSP_MCR_RPABLK_DEFAULT,
           MCBSP_MCR_RMCM_DEFAULT
           ),
        MCBSP_RCER_RMK(
           MCBSP_RCER_RCEB_DEFAULT,  /* All fields in RCER set to default values */
           MCBSP_RCER_RCEA_DEFAULT
           ),
	    MCBSP_XCER_RMK(
           MCBSP_XCER_XCEB_DEFAULT,  /* All fields in XCER set to default values */
           MCBSP_XCER_XCEA_DEFAULT
           ),
	    MCBSP_PCR_RMK(
           MCBSP_PCR_XIOEN_SP,
           MCBSP_PCR_RIOEN_SP,
           MCBSP_PCR_FSXM_INTERNAL, /* frame sync generation               */
           MCBSP_PCR_FSRM_EXTERNAL, 
           MCBSP_PCR_CLKXM_OUTPUT,  /* tans. clock mode from internal SRGR */
           MCBSP_PCR_CLKRM_INPUT,
           MCBSP_PCR_CLKSSTAT_0,
           MCBSP_PCR_DXSTAT_0,
           MCBSP_PCR_FSXP_ACTIVELOW, /* active low trans. frame sync. polarity  */
           MCBSP_PCR_FSRP_ACTIVELOW,
           MCBSP_PCR_CLKXP_RISING,  /* trans. clk pol. from rising edge of CLKX */
           MCBSP_PCR_CLKRP_FALLING
           )
			  };

	hMcbsp1 = MCBSP_open(MCBSP_DEV0,MCBSP_OPEN_RESET);
	MCBSP_reset(hMcbsp1);	//reset McBSP  
	MCBSP_config(hMcbsp1, &mcbspCfg);
	MCBSP_getConfig(hMcbsp1,&mcbspCfg1);


	puts("hi1!");
}

void MCBSP0init()
{
	extern MCBSP_Handle hMcbsp0;
	extern MCBSP_Config mcbspCfg0;
	Uint32 clkstpval;

	MCBSP_Config mcbspCfg = {
		MCBSP_SPCR_RMK(  
           MCBSP_SPCR_FREE_DEFAULT,
           MCBSP_SPCR_SOFT_DEFAULT,
           MCBSP_SPCR_FRST_DEFAULT,
           MCBSP_SPCR_GRST_DEFAULT,
           MCBSP_SPCR_XINTM_DEFAULT,
           MCBSP_SPCR_XSYNCERR_DEFAULT,
           MCBSP_SPCR_XRST_DEFAULT,
           MCBSP_SPCR_DLB_DEFAULT,
           MCBSP_SPCR_RJUST_DEFAULT,
           MCBSP_SPCR_CLKSTP_NODELAY, /* CLKSTP=10b with CLKXP=0, clock starts with */
           MCBSP_SPCR_DXENA_OFF,    /* rising edge without delay                     */
           MCBSP_SPCR_RINTM_DEFAULT,
           MCBSP_SPCR_RSYNCERR_DEFAULT,
           MCBSP_SPCR_RRST_DEFAULT
           ),
	    MCBSP_RCR_RMK(
           MCBSP_RCR_RPHASE_SINGLE,
           MCBSP_RCR_RFRLEN2_DEFAULT,
           MCBSP_RCR_RWDLEN2_DEFAULT,
           MCBSP_RCR_RCOMPAND_DEFAULT,
           MCBSP_RCR_RFIG_NO,
           MCBSP_RCR_RDATDLY_DEFAULT,
           MCBSP_RCR_RFRLEN1_DEFAULT,
           MCBSP_RCR_RWDLEN1_8BIT,  /* receive element length phase 1 is 8 bits */
           MCBSP_RCR_RWDREVRS_DISABLE
           ),
	    MCBSP_XCR_RMK(
           MCBSP_XCR_XPHASE_DEFAULT,
           MCBSP_XCR_XFRLEN2_DEFAULT,
           MCBSP_XCR_XWDLEN2_DEFAULT,
           MCBSP_XCR_XCOMPAND_DEFAULT,
           MCBSP_XCR_XFIG_DEFAULT,
           MCBSP_XCR_XDATDLY_DEFAULT,    /* 0 bit data delay                    */
           MCBSP_XCR_XFRLEN1_DEFAULT,
           MCBSP_XCR_XWDLEN1_8BIT,   /* transmit element phase 1 is 8 bits */
           MCBSP_XCR_XWDREVRS_DISABLE
           ),
		MCBSP_SRGR_RMK(
           MCBSP_SRGR_GSYNC_FREE,
           MCBSP_SRGR_CLKSP_RISING,
           MCBSP_SRGR_CLKSM_INTERNAL, /* SRGR clock mode from internal source */
           MCBSP_SRGR_FSGM_DEFAULT,
           MCBSP_SRGR_FPER_DEFAULT,
           MCBSP_SRGR_FWID_DEFAULT,
           MCBSP_SRGR_CLKGDV_OF(0x0A) /* divide clock by factor of 10         */
           ),
	    MCBSP_MCR_RMK(
           MCBSP_MCR_XPBBLK_DEFAULT, /* All fields in MCR set to default values    */
           MCBSP_MCR_XPABLK_DEFAULT,
           MCBSP_MCR_XMCM_DEFAULT,
           MCBSP_MCR_RPBBLK_DEFAULT,
           MCBSP_MCR_RPABLK_DEFAULT,
           MCBSP_MCR_RMCM_DEFAULT
           ),
        MCBSP_RCER_RMK(
           MCBSP_RCER_RCEB_DEFAULT,  /* All fields in RCER set to default values */
           MCBSP_RCER_RCEA_DEFAULT
           ),
	    MCBSP_XCER_RMK(
           MCBSP_XCER_XCEB_DEFAULT,  /* All fields in XCER set to default values */
           MCBSP_XCER_XCEA_DEFAULT
           ),
	    MCBSP_PCR_RMK(
           MCBSP_PCR_XIOEN_SP,
           MCBSP_PCR_RIOEN_SP,
           MCBSP_PCR_FSXM_EXTERNAL, /* frame sync generation               */
           MCBSP_PCR_FSRM_EXTERNAL, 
           MCBSP_PCR_CLKXM_INPUT,  /* tans. clock mode from external  */
           MCBSP_PCR_CLKRM_INPUT,
           MCBSP_PCR_CLKSSTAT_0,
           MCBSP_PCR_DXSTAT_0,
           MCBSP_PCR_FSXP_ACTIVELOW, /* active low trans. frame sync. polarity  */
           MCBSP_PCR_FSRP_ACTIVELOW,
           MCBSP_PCR_CLKXP_RISING,  /* trans. clk pol. from rising edge of CLKX */
           MCBSP_PCR_CLKRP_FALLING
           )
			  };


	hMcbsp0 = MCBSP_open(MCBSP_DEV0,MCBSP_OPEN_RESET);
	MCBSP_reset(hMcbsp0);
	MCBSP_config(hMcbsp0, &mcbspCfg);
	MCBSP_getConfig(hMcbsp0,&mcbspCfg0);
	puts("hi0!");	


}

void init()
{
	PLLinit();
//	L2cacheinit();
	MCBSP1init();
//	MCBSP0init();
}