yucca.c

Uboot源码,非常通用的bootloader.适用于各种平台的Linux系统引导.

	| IRQ 77  | PE1 BusMaster VCO                 | Falli | Edge  | Non   |
	| IRQ 78  | PE1 DCR Error                     | High  | Level | Non   |
	| IRQ 79  | Reserved                          | N/A   | N/A   | Non   |
	| IRQ 80  | PE2 AL                            | High  | Level | Non   |
	| IRQ 81  | PE2 VPD Access                    | Risin | Edge  | Non   |
	| IRQ 82  | PE2 Hot Reset Request             | Risin | Edge  | Non   |
	| IRQ 83  | PE2 Hot Reset Request             | Falli | Edge  | Non   |
	| IRQ 84  | PE2 TCR                           | High  | Level | Non   |
	| IRQ 85  | PE2 BusMaster VCO                 | Falli | Edge  | Non   |
	| IRQ 86  | PE2 DCR Error                     | High  | Level | Non   |
	| IRQ 87  | Reserved                          | N/A   | N/A   | Non   |
	| IRQ 88  | External IRQ(5)                   | Progr | Progr | Non   |
	| IRQ 89  | External IRQ 4 - Ethernet         | Progr | Progr | Non   |
	| IRQ 90  | External IRQ 3 - PCI-X            | Progr | Progr | Non   |
	| IRQ 91  | External IRQ 2 - PCI-X            | Progr | Progr | Non   |
	| IRQ 92  | External IRQ 1 - PCI-X            | Progr | Progr | Non   |
	| IRQ 93  | External IRQ 0 - PCI-X            | Progr | Progr | Non   |
	| IRQ 94  | Reserved                          | N/A   | N/A   | Non   |
	| IRQ 95  | Reserved                          | N/A   | N/A   | Non   |
	|---------------------------------------------------------------------
	| IRQ 96  | PE0 INTA                          | High  | Level | Non   |
	| IRQ 97  | PE0 INTB                          | High  | Level | Non   |
	| IRQ 98  | PE0 INTC                          | High  | Level | Non   |
	| IRQ 99  | PE0 INTD                          | High  | Level | Non   |
	| IRQ 100 | PE1 INTA                          | High  | Level | Non   |
	| IRQ 101 | PE1 INTB                          | High  | Level | Non   |
	| IRQ 102 | PE1 INTC                          | High  | Level | Non   |
	| IRQ 103 | PE1 INTD                          | High  | Level | Non   |
	| IRQ 104 | PE2 INTA                          | High  | Level | Non   |
	| IRQ 105 | PE2 INTB                          | High  | Level | Non   |
	| IRQ 106 | PE2 INTC                          | High  | Level | Non   |
	| IRQ 107 | PE2 INTD                          | Risin | Edge  | Non   |
	| IRQ 108 | PCI Express MSI Level 4           | Risin | Edge  | Non   |
	| IRQ 109 | PCI Express MSI Level 5           | Risin | Edge  | Non   |
	| IRQ 110 | PCI Express MSI Level 6           | Risin | Edge  | Non   |
	| IRQ 111 | PCI Express MSI Level 7           | Risin | Edge  | Non   |
	| IRQ 116 | PCI Express MSI Level 12          | Risin | Edge  | Non   |
	| IRQ 112 | PCI Express MSI Level 8           | Risin | Edge  | Non   |
	| IRQ 113 | PCI Express MSI Level 9           | Risin | Edge  | Non   |
	| IRQ 114 | PCI Express MSI Level 10          | Risin | Edge  | Non   |
	| IRQ 115 | PCI Express MSI Level 11          | Risin | Edge  | Non   |
	| IRQ 117 | PCI Express MSI Level 13          | Risin | Edge  | Non   |
	| IRQ 118 | PCI Express MSI Level 14          | Risin | Edge  | Non   |
	| IRQ 119 | PCI Express MSI Level 15          | Risin | Edge  | Non   |
	| IRQ 120 | PCI Express MSI Level 16          | Risin | Edge  | Non   |
	| IRQ 121 | PCI Express MSI Level 17          | Risin | Edge  | Non   |
	| IRQ 122 | PCI Express MSI Level 18          | Risin | Edge  | Non   |
	| IRQ 123 | PCI Express MSI Level 19          | Risin | Edge  | Non   |
	| IRQ 124 | PCI Express MSI Level 20          | Risin | Edge  | Non   |
	| IRQ 125 | PCI Express MSI Level 21          | Risin | Edge  | Non   |
	| IRQ 126 | PCI Express MSI Level 22          | Risin | Edge  | Non   |
	| IRQ 127 | PCI Express MSI Level 23          | Risin | Edge  | Non   |
	+---------+-----------------------------------+-------+-------+------*/
	/*--------------------------------------------------------------------+
	 | Put UICs in PowerPC440SPemode.
	 | Initialise UIC registers.  Clear all interrupts.  Disable all
	 | interrupts.
	 | Set critical interrupt values.  Set interrupt polarities.  Set
	 | interrupt trigger levels.  Make bit 0 High  priority.  Clear all
	 | interrupts again.
	 +-------------------------------------------------------------------*/
	mtdcr (uic3sr, 0xffffffff);	/* Clear all interrupts */
	mtdcr (uic3er, 0x00000000);	/* disable all interrupts */
	mtdcr (uic3cr, 0x00000000);	/* Set Critical / Non Critical
					 * interrupts */
	mtdcr (uic3pr, 0xffffffff);	/* Set Interrupt Polarities */
	mtdcr (uic3tr, 0x001fffff);	/* Set Interrupt Trigger Levels */
	mtdcr (uic3vr, 0x00000001);	/* Set Vect base=0,INT31 Highest
					 * priority */
	mtdcr (uic3sr, 0x00000000);	/* clear all  interrupts */
	mtdcr (uic3sr, 0xffffffff);	/* clear all  interrupts */

	mtdcr (uic2sr, 0xffffffff);	/* Clear all interrupts */
	mtdcr (uic2er, 0x00000000);	/* disable all interrupts */
	mtdcr (uic2cr, 0x00000000);	/* Set Critical / Non Critical
					 * interrupts */
	mtdcr (uic2pr, 0xebebebff);	/* Set Interrupt Polarities */
	mtdcr (uic2tr, 0x74747400);	/* Set Interrupt Trigger Levels */
	mtdcr (uic2vr, 0x00000001);	/* Set Vect base=0,INT31 Highest
					 * priority */
	mtdcr (uic2sr, 0x00000000);	/* clear all interrupts */
	mtdcr (uic2sr, 0xffffffff);	/* clear all interrupts */

	mtdcr (uic1sr, 0xffffffff);	/* Clear all interrupts */
	mtdcr (uic1er, 0x00000000);	/* disable all interrupts */
	mtdcr (uic1cr, 0x00000000);	/* Set Critical / Non Critical
					 * interrupts */
	mtdcr (uic1pr, 0xffffffff);	/* Set Interrupt Polarities */
	mtdcr (uic1tr, 0x001f8040);	/* Set Interrupt Trigger Levels */
	mtdcr (uic1vr, 0x00000001);	/* Set Vect base=0,INT31 Highest
					 * priority */
	mtdcr (uic1sr, 0x00000000);	/* clear all interrupts */
	mtdcr (uic1sr, 0xffffffff);	/* clear all interrupts */

	mtdcr (uic0sr, 0xffffffff);	/* Clear all interrupts */
	mtdcr (uic0er, 0x00000000);	/* disable all interrupts excepted
					 * cascade to be checked */
	mtdcr (uic0cr, 0x00104001);	/* Set Critical / Non Critical
					 * interrupts */
	mtdcr (uic0pr, 0xffffffff);	/* Set Interrupt Polarities */
	mtdcr (uic0tr, 0x010f0004);	/* Set Interrupt Trigger Levels */
	mtdcr (uic0vr, 0x00000001);	/* Set Vect base=0,INT31 Highest
					 * priority */
	mtdcr (uic0sr, 0x00000000);	/* clear all interrupts */
	mtdcr (uic0sr, 0xffffffff);	/* clear all interrupts */

	/* SDR0_MFR should be part of Ethernet init */
	mfsdr (sdr_mfr, mfr);
	mfr &= ~SDR0_MFR_ECS_MASK;
	/*mtsdr(sdr_mfr, mfr);*/
	fpga_init();

	return 0;
}

int checkboard (void)
{
	char *s = getenv("serial#");

	printf("Board: Yucca - AMCC 440SPe Evaluation Board");
	if (s != NULL) {
		puts(", serial# ");
		puts(s);
	}
	putc('\n');

	return 0;
}

static long int yucca_probe_for_dimms(void)
{
	int 	dimm_installed[MAXDIMMS];
	int	dimm_num, result;
	int	dimms_found = 0;
	uchar	dimm_addr = IIC0_DIMM0_ADDR;
	uchar   dimm_spd_data[MAX_SPD_BYTES];

	for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
		/* check if there is a chip at the dimm address	*/
		switch (dimm_num) {
			case 0:
				dimm_addr = IIC0_DIMM0_ADDR;
				break;
			case 1:
				dimm_addr = IIC0_DIMM1_ADDR;
				break;
		}

		result = i2c_probe(dimm_addr);

		memset(dimm_spd_data, 0, MAX_SPD_BYTES * sizeof(char));
		if (result == 0) {
			/* read first byte of SPD data, if there is any data */
			result = i2c_read(dimm_addr, 0, 1, dimm_spd_data, 1);

			if (result == 0) {
				result = dimm_spd_data[0];
				result = result > MAX_SPD_BYTES ?
						MAX_SPD_BYTES : result;
				result = i2c_read(dimm_addr, 0, 1,
							dimm_spd_data, result);
			}
		}

		if ((result == 0) &&
		    (dimm_spd_data[64] == MICRON_SPD_JEDEC_ID)) {
			dimm_installed[dimm_num] = TRUE;
			dimms_found++;
			debug("DIMM slot %d: DDR2 SDRAM detected\n", dimm_num);
		} else {
			dimm_installed[dimm_num] = FALSE;
			debug("DIMM slot %d: Not populated or cannot sucessfully probe the DIMM\n", dimm_num);
		}
	}

	if (dimms_found == 0) {
		printf("ERROR - No memory installed.  Install a DDR-SDRAM DIMM.\n\n");
		hang();
	}

	if (dimm_installed[0] != TRUE) {
		printf("\nERROR - DIMM slot 0 must be populated before DIMM slot 1.\n");
		printf("        Unsupported configuration. Move DIMM module from DIMM slot 1 to slot 0.\n\n");
		hang();
	}

	return dimms_found;
}

/*************************************************************************
 * init SDRAM controller with fixed value
 * the initialization values are for 2x MICRON DDR2
 * PN: MT18HTF6472DY-53EB2
 * 512MB, DDR2, 533, CL4, ECC, REG
 ************************************************************************/
static long int fixed_sdram(void)
{
	long int yucca_dimms = 0;

	yucca_dimms = yucca_probe_for_dimms();

	/* SDRAM0_MCOPT2 (0X21) Clear DCEN BIT	*/
	mtdcr( 0x10, 0x00000021 );
	mtdcr( 0x11, 0x84000000 );

	/* SDRAM0_MCOPT1 (0X20) ECC OFF / 64 bits / 4 banks / DDR2	*/
	mtdcr( 0x10, 0x00000020 );
	mtdcr( 0x11, 0x2D122000 );

	/* SET MCIF0_CODT   Die Termination On	*/
	mtdcr( 0x10, 0x00000026 );
	if (yucca_dimms == 2)
		mtdcr( 0x11, 0x2A800021 );
	else if (yucca_dimms == 1)
		mtdcr( 0x11, 0x02800021 );

	/* On-Die Termination for Bank 0	*/
	mtdcr( 0x10, 0x00000022 );
	if (yucca_dimms == 2)
		mtdcr( 0x11, 0x18000000 );
	else if (yucca_dimms == 1)
		mtdcr( 0x11, 0x06000000 );

	/*	On-Die Termination for Bank 1	*/
	mtdcr( 0x10, 0x00000023 );
	if (yucca_dimms == 2)
		mtdcr( 0x11, 0x18000000 );
	else if (yucca_dimms == 1)
		mtdcr( 0x11, 0x01800000 );

	/*	On-Die Termination for Bank 2	*/
	mtdcr( 0x10, 0x00000024 );
	if (yucca_dimms == 2)
		mtdcr( 0x11, 0x01800000 );
	else if (yucca_dimms == 1)
		mtdcr( 0x11, 0x00000000 );

	/*	On-Die Termination for Bank 3	*/
	mtdcr( 0x10, 0x00000025 );
	if (yucca_dimms == 2)
		mtdcr( 0x11, 0x01800000 );
	else if (yucca_dimms == 1)
		mtdcr( 0x11, 0x00000000 );

	/* Refresh Time register (0x30) Refresh every 7.8125uS	*/
	mtdcr( 0x10, 0x00000030 );
	mtdcr( 0x11, 0x08200000 );

	/* SET MCIF0_MMODE  	 CL 4	*/
	mtdcr( 0x10, 0x00000088 );
	mtdcr( 0x11, 0x00000642 );

	/* MCIF0_MEMODE	*/
	mtdcr( 0x10, 0x00000089 );
	mtdcr( 0x11, 0x00000004 );

	/*SET MCIF0_MB0CF 	*/
	mtdcr( 0x10, 0x00000040 );
	mtdcr( 0x11, 0x00000201 );

	/* SET MCIF0_MB1CF 	*/
	mtdcr( 0x10, 0x00000044 );
	mtdcr( 0x11, 0x00000201 );

	/* SET MCIF0_MB2CF 	*/
	mtdcr( 0x10, 0x00000048 );
	if (yucca_dimms == 2)
		mtdcr( 0x11, 0x00000201 );
	else if (yucca_dimms == 1)
		mtdcr( 0x11, 0x00000000 );

	/* SET MCIF0_MB3CF 	*/
	mtdcr( 0x10, 0x0000004c );
	if (yucca_dimms == 2)
		mtdcr( 0x11, 0x00000201 );
	else if (yucca_dimms == 1)
		mtdcr( 0x11, 0x00000000 );

	/* SET MCIF0_INITPLR0  # NOP		*/
	mtdcr( 0x10, 0x00000050 );
	mtdcr( 0x11, 0xB5380000 );

	/* SET MCIF0_INITPLR1  # PRE		*/
	mtdcr( 0x10, 0x00000051 );
	mtdcr( 0x11, 0x82100400 );

	/* SET MCIF0_INITPLR2  # EMR2		*/
	mtdcr( 0x10, 0x00000052 );
	mtdcr( 0x11, 0x80820000 );

	/* SET MCIF0_INITPLR3  # EMR3		*/
	mtdcr( 0x10, 0x00000053 );
	mtdcr( 0x11, 0x80830000 );

	/* SET MCIF0_INITPLR4  # EMR DLL ENABLE	*/
	mtdcr( 0x10, 0x00000054 );
	mtdcr( 0x11, 0x80810000 );

	/* SET MCIF0_INITPLR5  # MR DLL RESET	*/
	mtdcr( 0x10, 0x00000055 );
	mtdcr( 0x11, 0x80800542 );

	/* SET MCIF0_INITPLR6  # PRE		*/
	mtdcr( 0x10, 0x00000056 );
	mtdcr( 0x11, 0x82100400 );

	/* SET MCIF0_INITPLR7  # Refresh	*/
	mtdcr( 0x10, 0x00000057 );
	mtdcr( 0x11, 0x8A080000 );

	/* SET MCIF0_INITPLR8  # Refresh	*/
	mtdcr( 0x10, 0x00000058 );
	mtdcr( 0x11, 0x8A080000 );

	/* SET MCIF0_INITPLR9  # Refresh	*/
	mtdcr( 0x10, 0x00000059 );
	mtdcr( 0x11, 0x8A080000 );

	/* SET MCIF0_INITPLR10 # Refresh	*/
	mtdcr( 0x10, 0x0000005A );
	mtdcr( 0x11, 0x8A080000 );

	/* SET MCIF0_INITPLR11 # MR		*/
	mtdcr( 0x10, 0x0000005B );
	mtdcr( 0x11, 0x80800442 );

	/* SET MCIF0_INITPLR12 # EMR OCD Default*/
	mtdcr( 0x10, 0x0000005C );
	mtdcr( 0x11, 0x80810380 );

	/* SET MCIF0_INITPLR13 # EMR OCD Exit	*/
	mtdcr( 0x10, 0x0000005D );
	mtdcr( 0x11, 0x80810000 );

	/* 0x80: Adv Addr clock by 180 deg	*/
	mtdcr( 0x10, 0x00000080 );
	mtdcr( 0x11, 0x80000000 );

	/* 0x21: Exit self refresh, set DC_EN	*/
	mtdcr( 0x10, 0x00000021 );
	mtdcr( 0x11, 0x28000000 );

	/* 0x81: Write DQS Adv 90 + Fractional DQS Delay	*/
	mtdcr( 0x10, 0x00000081 );
	mtdcr( 0x11, 0x80000800 );

	/* MCIF0_SDTR1	*/
	mtdcr( 0x10, 0x00000085 );
	mtdcr( 0x11, 0x80201000 );

	/* MCIF0_SDTR2	*/
	mtdcr( 0x10, 0x00000086 );
	mtdcr( 0x11, 0x42103242 );

	/* MCIF0_SDTR3	*/
	mtdcr( 0x10, 0x00000087 );
	mtdcr( 0x11, 0x0C100D14 );

	/* SET MQ0_B0BAS  base addr 00000000 / 256MB	*/
	mtdcr( 0x40, 0x0000F800 );

	/* SET MQ0_B1BAS  base addr 10000000 / 256MB	*/
	mtdcr( 0x41, 0x0400F800 );

	/* SET MQ0_B2BAS  base addr 20000000 / 256MB	*/
	if (yucca_dimms == 2)
		mtdcr( 0x42, 0x0800F800 );
	else if (yucca_dimms == 1)
		mtdcr( 0x42, 0x00000000 );

	/* SET MQ0_B3BAS  base addr 30000000 / 256MB	*/
	if (yucca_dimms == 2)
		mtdcr( 0x43, 0x0C00F800 );
	else if (yucca_dimms == 1)
		mtdcr( 0x43, 0x00000000 );

	/* SDRAM_RQDC	*/
	mtdcr( 0x10, 0x00000070 );
	mtdcr( 0x11, 0x8000003F );

	/* SDRAM_RDCC	*/
	mtdcr( 0x10, 0x00000078 );
	mtdcr( 0x11, 0x80000000 );

	/* SDRAM_RFDC	*/
	mtdcr( 0x10, 0x00000074 );
	mtdcr( 0x11, 0x00000220 );

	return (yucca_dimms * 512) << 20;
}

long int initdram (int board_type)
{
	long dram_size = 0;

	dram_size = fixed_sdram();

	return dram_size;
}

#if defined(CFG_DRAM_TEST)
int testdram (void)
{
	uint *pstart = (uint *) 0x00000000;
	uint *pend = (uint *) 0x08000000;
	uint *p;

	for (p = pstart; p < pend; p++)
		*p = 0xaaaaaaaa;

	for (p = pstart; p < pend; p++) {
		if (*p != 0xaaaaaaaa) {
			printf ("SDRAM test fails at: %08x\n", (uint) p);
			return 1;
		}
	}

	for (p = pstart; p < pend; p++)
		*p = 0x55555555;

	for (p = pstart; p < pend; p++) {
		if (*p != 0x55555555) {
			printf ("SDRAM test fails at: %08x\n", (uint) p);
			return 1;
		}
	}
	return 0;
}
#endif

/*************************************************************************
 *  pci_pre_init
 *
 *  This routine is called just prior to registering the hose and gives
 *  the board the opportunity to check things. Returning a value of zero
 *  indicates that things are bad & PCI initialization should be aborted.
 *