mycpu.map.eqn

Quartus II 5.0下写的一个单总线架构的CPU设计

Z1_q_a[1]_PORT_A_data_in = K2L9;
Z1_q_a[1]_PORT_A_data_in_reg = DFFE(Z1_q_a[1]_PORT_A_data_in, Z1_q_a[1]_clock_0, , , );
Z1_q_a[1]_PORT_A_address = BUS(B5_19, B5_18, B5_17, B5_16, B5_15, B5_14, B5_13, B5_12);
Z1_q_a[1]_PORT_A_address_reg = DFFE(Z1_q_a[1]_PORT_A_address, Z1_q_a[1]_clock_0, , , );
Z1_q_a[1]_PORT_B_address = BUS(B5_19, B5_18, B5_17, B5_16, B5_15, B5_14, B5_13, B5_12);
Z1_q_a[1]_PORT_B_address_reg = DFFE(Z1_q_a[1]_PORT_B_address, Z1_q_a[1]_clock_0, , , );
Z1_q_a[1]_PORT_A_write_enable = 70;
Z1_q_a[1]_PORT_A_write_enable_reg = DFFE(Z1_q_a[1]_PORT_A_write_enable, Z1_q_a[1]_clock_0, , , );
Z1_q_a[1]_clock_0 = CLK;
Z1_q_a[1]_PORT_A_data_out = MEMORY(Z1_q_a[1]_PORT_A_data_in_reg, , Z1_q_a[1]_PORT_A_address_reg, Z1_q_a[1]_PORT_B_address_reg, Z1_q_a[1]_PORT_A_write_enable_reg, , , , Z1_q_a[1]_clock_0, , , , , );
Z1_q_a[1]_PORT_A_data_out_reg = DFFE(Z1_q_a[1]_PORT_A_data_out, Z1_q_a[1]_clock_0, , , );
Z1_q_a[1] = Z1_q_a[1]_PORT_A_data_out_reg[0];


--S4L3 is 8cpu:92|busmux:49|lpm_mux:$00000|mux_afc:auto_generated|w_result25w~16
--operation mode is normal

S4L3 = S4L51 & (S4L61) # !S4L51 & (S4L61 & B9_18 # !S4L61 & (Z1_q_a[1]));


--S4L4 is 8cpu:92|busmux:49|lpm_mux:$00000|mux_afc:auto_generated|w_result25w~17
--operation mode is normal

S4L4 = S4L51 & (S4L3 & (kdata[2]) # !S4L3 & X2L02) # !S4L51 & (S4L3);


--K2L7 is 8cpu:92|pc:65|74161:8|f74161:sub|85~0
--operation mode is arithmetic

K2L7_carry_eqn = K2_81;
K2L7 = K2_87 $ (K2L7_carry_eqn);

--K2_85 is 8cpu:92|pc:65|74161:8|f74161:sub|85
--operation mode is arithmetic

K2_85 = CARRY(!K2_81 # !K2_87);


--B9_19 is 8cpu:92|alu:62|74273b:11|19
--operation mode is normal

B9_19_lut_out = W3L61;
B9_19 = DFFEAS(B9_19_lut_out, M1_22, VCC, , , , , , );


--X2L71 is 8cpu:92|bi74670:67|74670c:34|107~11
--operation mode is normal

X2L71 = 69 & (68) # !69 & (68 & X2_20 # !68 & (X2_5));


--X2L81 is 8cpu:92|bi74670:67|74670c:34|107~12
--operation mode is normal

X2L81 = 69 & (X2L71 & (X2_29) # !X2L71 & X2_19) # !69 & (X2L71);


--Z1_q_a[0] is 8cpu:92|lpm_ram_dq0:inst|altsyncram:altsyncram_component|altsyncram_rs21:auto_generated|q_a[0]
--RAM Block Operation Mode: Single Port
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
Z1_q_a[0]_PORT_A_data_in = K2L2;
Z1_q_a[0]_PORT_A_data_in_reg = DFFE(Z1_q_a[0]_PORT_A_data_in, Z1_q_a[0]_clock_0, , , );
Z1_q_a[0]_PORT_A_address = BUS(B5_19, B5_18, B5_17, B5_16, B5_15, B5_14, B5_13, B5_12);
Z1_q_a[0]_PORT_A_address_reg = DFFE(Z1_q_a[0]_PORT_A_address, Z1_q_a[0]_clock_0, , , );
Z1_q_a[0]_PORT_B_address = BUS(B5_19, B5_18, B5_17, B5_16, B5_15, B5_14, B5_13, B5_12);
Z1_q_a[0]_PORT_B_address_reg = DFFE(Z1_q_a[0]_PORT_B_address, Z1_q_a[0]_clock_0, , , );
Z1_q_a[0]_PORT_A_write_enable = 70;
Z1_q_a[0]_PORT_A_write_enable_reg = DFFE(Z1_q_a[0]_PORT_A_write_enable, Z1_q_a[0]_clock_0, , , );
Z1_q_a[0]_clock_0 = CLK;
Z1_q_a[0]_PORT_A_data_out = MEMORY(Z1_q_a[0]_PORT_A_data_in_reg, , Z1_q_a[0]_PORT_A_address_reg, Z1_q_a[0]_PORT_B_address_reg, Z1_q_a[0]_PORT_A_write_enable_reg, , , , Z1_q_a[0]_clock_0, , , , , );
Z1_q_a[0]_PORT_A_data_out_reg = DFFE(Z1_q_a[0]_PORT_A_data_out, Z1_q_a[0]_clock_0, , , );
Z1_q_a[0] = Z1_q_a[0]_PORT_A_data_out_reg[0];


--S4L1 is 8cpu:92|busmux:49|lpm_mux:$00000|mux_afc:auto_generated|w_result11w~16
--operation mode is normal

S4L1 = S4L61 & (S4L51) # !S4L61 & (S4L51 & X2L81 # !S4L51 & (Z1_q_a[0]));


--S4L2 is 8cpu:92|busmux:49|lpm_mux:$00000|mux_afc:auto_generated|w_result11w~17
--operation mode is normal

S4L2 = S4L61 & (S4L1 & (kdata[1]) # !S4L1 & B9_19) # !S4L61 & (S4L1);


--K2L4 is 8cpu:92|pc:65|74161:8|f74161:sub|81~0
--operation mode is arithmetic

K2L4 = K2_9;

--K2_81 is 8cpu:92|pc:65|74161:8|f74161:sub|81
--operation mode is arithmetic

K2_81 = CARRY(K2_9);


--17 is 17
--operation mode is normal

17 = H1_37 & CLK;


--19 is 19
--operation mode is normal

19 = H1_33 & B2_14 & CLK;


--76 is 76
--operation mode is normal

76 = H1_35 & B4_18 # !CLRN;


--M1_21 is 8cpu:92|alu:62|21
--operation mode is normal

M1_21 = H1_33 & B1_17 & CLK;


--M1_18 is 8cpu:92|alu:62|18
--operation mode is normal

M1_18 = H1_33 & B1_16 & CLK;


--B8_13 is 8cpu:92|alu:62|74273b:5|13
--operation mode is normal

B8_13_lut_out = K3L51;
B8_13 = DFFEAS(B8_13_lut_out, M1_21, VCC, , , , , , );


--B7_13 is 8cpu:92|alu:62|74273b:4|13
--operation mode is normal

B7_13_lut_out = K3L51;
B7_13 = DFFEAS(B7_13_lut_out, M1_18, VCC, , , , , , );


--W3L6 is 8cpu:92|alu:62|lpm_add_sub:1|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~166
--operation mode is arithmetic

W3L6_carry_eqn = W3L9;
W3L6 = B8_14 $ B7_14 $ W3L6_carry_eqn;

--W3L7 is 8cpu:92|alu:62|lpm_add_sub:1|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~168
--operation mode is arithmetic

W3L7 = CARRY(B8_14 & !B7_14 & !W3L9 # !B8_14 & (!W3L9 # !B7_14));


--X1L41 is 8cpu:92|bi74670:67|74670c:32|82~36
--operation mode is normal

X1L41 = B3_17 & (!B3_16);


--93 is 93
--operation mode is normal

93 = H1_33 & B2_18;


--X1_85 is 8cpu:92|bi74670:67|74670c:32|85
--operation mode is normal

X1_85 = X1L41 & (93 & K3L81 # !93 & (X1_85)) # !X1L41 & (X1_85);


--X1L51 is 8cpu:92|bi74670:67|74670c:32|82~37
--operation mode is normal

X1L51 = B3_16 & (!B3_17);


--X1_86 is 8cpu:92|bi74670:67|74670c:32|86
--operation mode is normal

X1_86 = X1L51 & (93 & K3L81 # !93 & (X1_86)) # !X1L51 & (X1_86);


--X1L91 is 8cpu:92|bi74670:67|74670c:32|92~3
--operation mode is normal

X1L91 = B3_17 # B3_16;


--X1_95 is 8cpu:92|bi74670:67|74670c:32|95
--operation mode is normal

X1_95 = X1L91 & (X1_95) # !X1L91 & (93 & K3L81 # !93 & (X1_95));


--X1L61 is 8cpu:92|bi74670:67|74670c:32|82~38
--operation mode is normal

X1L61 = B3_17 & B3_16;


--X1_76 is 8cpu:92|bi74670:67|74670c:32|76
--operation mode is normal

X1_76 = X1L61 & (93 & K3L81 # !93 & (X1_76)) # !X1L61 & (X1_76);


--M1_22 is 8cpu:92|alu:62|22
--operation mode is normal

M1_22 = H1_35 & B1_18 & CLK;


--70 is 70
--operation mode is normal

70 = H1_33 & B2_17;


--B5_19 is 8cpu:92|74273b:3|19
--operation mode is normal

B5_19_lut_out = K2L2;
B5_19 = DFFEAS(B5_19_lut_out, G1_14, VCC, , , , , , );


--B5_18 is 8cpu:92|74273b:3|18
--operation mode is normal

B5_18_lut_out = K2L9;
B5_18 = DFFEAS(B5_18_lut_out, G1_14, VCC, , , , , , );


--B5_17 is 8cpu:92|74273b:3|17
--operation mode is normal

B5_17_lut_out = K2L31;
B5_17 = DFFEAS(B5_17_lut_out, G1_14, VCC, , , , , , );


--B5_16 is 8cpu:92|74273b:3|16
--operation mode is normal

B5_16_lut_out = K2L71;
B5_16 = DFFEAS(B5_16_lut_out, G1_14, VCC, , , , , , );


--B5_15 is 8cpu:92|74273b:3|15
--operation mode is normal

B5_15_lut_out = K3L2;
B5_15 = DFFEAS(B5_15_lut_out, G1_14, VCC, , , , , , );


--B5_14 is 8cpu:92|74273b:3|14
--operation mode is normal

B5_14_lut_out = K3L11;
B5_14 = DFFEAS(B5_14_lut_out, G1_14, VCC, , , , , , );


--B5_13 is 8cpu:92|74273b:3|13
--operation mode is normal

B5_13_lut_out = K3L51;
B5_13 = DFFEAS(B5_13_lut_out, G1_14, VCC, , , , , , );


--B5_12 is 8cpu:92|74273b:3|12
--operation mode is normal

B5_12_lut_out = K3L81;
B5_12 = DFFEAS(B5_12_lut_out, G1_14, VCC, , , , , , );


--K3_107 is 8cpu:92|pc:65|74161:9|f74161:sub|107
--operation mode is normal

K3_107_carry_eqn = K3_95;
K3_107 = K3_110 $ (!K3_107_carry_eqn & K3L7);


--X1_65 is 8cpu:92|bi74670:67|74670c:32|65
--operation mode is normal

X1_65 = X1L51 & (93 & K3L51 # !93 & (X1_65)) # !X1L51 & (X1_65);


--X1_66 is 8cpu:92|bi74670:67|74670c:32|66
--operation mode is normal

X1_66 = X1L41 & (93 & K3L51 # !93 & (X1_66)) # !X1L41 & (X1_66);


--X1_56 is 8cpu:92|bi74670:67|74670c:32|56
--operation mode is normal

X1_56 = X1L91 & (X1_56) # !X1L91 & (93 & K3L51 # !93 & (X1_56));


--X1_75 is 8cpu:92|bi74670:67|74670c:32|75
--operation mode is normal

X1_75 = X1L61 & (93 & K3L51 # !93 & (X1_75)) # !X1L61 & (X1_75);


--X1_39 is 8cpu:92|bi74670:67|74670c:32|39
--operation mode is normal

X1_39 = X1L41 & (93 & K3L11 # !93 & (X1_39)) # !X1L41 & (X1_39);


--X1_40 is 8cpu:92|bi74670:67|74670c:32|40
--operation mode is normal

X1_40 = X1L51 & (93 & K3L11 # !93 & (X1_40)) # !X1L51 & (X1_40);


--X1_51 is 8cpu:92|bi74670:67|74670c:32|51
--operation mode is normal

X1_51 = X1L91 & (X1_51) # !X1L91 & (93 & K3L11 # !93 & (X1_51));


--X1_30 is 8cpu:92|bi74670:67|74670c:32|30
--operation mode is normal

X1_30 = X1L61 & (93 & K3L11 # !93 & (X1_30)) # !X1L61 & (X1_30);


--W3L8 is 8cpu:92|alu:62|lpm_add_sub:1|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~171
--operation mode is arithmetic

W3L8_carry_eqn = W3L11;
W3L8 = B8_15 $ B7_15 $ !W3L8_carry_eqn;

--W3L9 is 8cpu:92|alu:62|lpm_add_sub:1|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~173
--operation mode is arithmetic

W3L9 = CARRY(B8_15 & (B7_15 # !W3L11) # !B8_15 & B7_15 & !W3L11);


--X1_19 is 8cpu:92|bi74670:67|74670c:32|19
--operation mode is normal

X1_19 = X1L51 & (93 & K3L2 # !93 & (X1_19)) # !X1L51 & (X1_19);


--X1_20 is 8cpu:92|bi74670:67|74670c:32|20
--operation mode is normal

X1_20 = X1L41 & (93 & K3L2 # !93 & (X1_20)) # !X1L41 & (X1_20);


--X1_5 is 8cpu:92|bi74670:67|74670c:32|5
--operation mode is normal

X1_5 = X1L91 & (X1_5) # !X1L91 & (93 & K3L2 # !93 & (X1_5));


--X1_29 is 8cpu:92|bi74670:67|74670c:32|29
--operation mode is normal

X1_29 = X1L61 & (93 & K3L2 # !93 & (X1_29)) # !X1L61 & (X1_29);


--X2_85 is 8cpu:92|bi74670:67|74670c:34|85
--operation mode is normal

X2_85 = X1L41 & (93 & K2L71 # !93 & (X2_85)) # !X1L41 & (X2_85);


--X2_86 is 8cpu:92|bi74670:67|74670c:34|86
--operation mode is normal

X2_86 = X1L51 & (93 & K2L71 # !93 & (X2_86)) # !X1L51 & (X2_86);


--X2_95 is 8cpu:92|bi74670:67|74670c:34|95
--operation mode is normal

X2_95 = X1L91 & (X2_95) # !X1L91 & (93 & K2L71 # !93 & (X2_95));


--X2_76 is 8cpu:92|bi74670:67|74670c:34|76
--operation mode is normal

X2_76 = X1L61 & (93 & K2L71 # !93 & (X2_76)) # !X1L61 & (X2_76);


--W3L01 is 8cpu:92|alu:62|lpm_add_sub:1|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~176
--operation mode is arithmetic

W3L01_carry_eqn = W3L31;
W3L01 = B8_16 $ B7_16 $ W3L01_carry_eqn;

--W3L11 is 8cpu:92|alu:62|lpm_add_sub:1|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~178
--operation mode is arithmetic

W3L11 = CARRY(B8_16 & !B7_16 & !W3L31 # !B8_16 & (!W3L31 # !B7_16));


--W3L21 is 8cpu:92|alu:62|lpm_add_sub:1|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~181
--operation mode is arithmetic

W3L21_carry_eqn = W3L51;
W3L21 = B8_17 $ B7_17 $ !W3L21_carry_eqn;

--W3L31 is 8cpu:92|alu:62|lpm_add_sub:1|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~183
--operation mode is arithmetic

W3L31 = CARRY(B8_17 & (B7_17 # !W3L51) # !B8_17 & B7_17 & !W3L51);


--X2_65 is 8cpu:92|bi74670:67|74670c:34|65
--operation mode is normal

X2_65 = X1L51 & (93 & K2L31 # !93 & (X2_65)) # !X1L51 & (X2_65);


--X2_66 is 8cpu:92|bi74670:67|74670c:34|66
--operation mode is normal

X2_66 = X1L41 & (93 & K2L31 # !93 & (X2_66)) # !X1L41 & (X2_66);


--X2_56 is 8cpu:92|bi74670:67|74670c:34|56
--operation mode is normal

X2_56 = X1L91 & (X2_56) # !X1L91 & (93 & K2L31 # !93 & (X2_56));


--X2_75 is 8cpu:92|bi74670:67|74670c:34|75
--operation mode is normal

X2_75 = X1L61 & (93 & K2L31 # !93 & (X2_75)) # !X1L61 & (X2_75);


--X2_39 is 8cpu:92|bi74670:67|74670c:34|39