mycpu.map.eqn

Quartus II 5.0下写的一个单总线架构的CPU设计

--operation mode is normal

B3_19_lut_out = K2L2;
B3_19 = DFFEAS(B3_19_lut_out, 19, !76, , , , , , );


--B3_17 is 74273b:10|17
--operation mode is normal

B3_17_lut_out = K2L31;
B3_17 = DFFEAS(B3_17_lut_out, 19, !76, , , , , , );


--68 is 68
--operation mode is normal

68 = B2_15 & (B3_17 # B2_16 & B3_19) # !B2_15 & B2_16 & B3_19;


--B3_18 is 74273b:10|18
--operation mode is normal

B3_18_lut_out = K2L9;
B3_18 = DFFEAS(B3_18_lut_out, 19, !76, , , , , , );


--B3_16 is 74273b:10|16
--operation mode is normal

B3_16_lut_out = K2L71;
B3_16 = DFFEAS(B3_16_lut_out, 19, !76, , , , , , );


--69 is 69
--operation mode is normal

69 = B2_15 & (B3_16 # B2_16 & B3_18) # !B2_15 & B2_16 & B3_18;


--X1L72 is 8cpu:92|bi74670:67|74670c:32|126~11
--operation mode is normal

X1L72 = 68 & (69) # !68 & (69 & X1_86 # !69 & (X1_95));


--X1L82 is 8cpu:92|bi74670:67|74670c:32|126~12
--operation mode is normal

X1L82 = 68 & (X1L72 & (X1_76) # !X1L72 & X1_85) # !68 & (X1L72);


--S4L51 is 8cpu:92|busmux:49|lpm_mux:$00000|mux_afc:auto_generated|w_result97w~86
--operation mode is normal

S4L51 = H1_33 & (B1_15 # B1_12 & B1_13);


--B9_12 is 8cpu:92|alu:62|74273b:11|12
--operation mode is normal

B9_12_lut_out = W3L2;
B9_12 = DFFEAS(B9_12_lut_out, M1_22, VCC, , , , , , );


--S4L61 is 8cpu:92|busmux:49|lpm_mux:$00000|mux_afc:auto_generated|w_result97w~87
--operation mode is normal

S4L61 = H1_33 & B1_13 & (!B1_15);


--Z1_q_a[7] is 8cpu:92|lpm_ram_dq0:inst|altsyncram:altsyncram_component|altsyncram_rs21:auto_generated|q_a[7]
--RAM Block Operation Mode: Single Port
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
Z1_q_a[7]_PORT_A_data_in = K3L81;
Z1_q_a[7]_PORT_A_data_in_reg = DFFE(Z1_q_a[7]_PORT_A_data_in, Z1_q_a[7]_clock_0, , , );
Z1_q_a[7]_PORT_A_address = BUS(B5_19, B5_18, B5_17, B5_16, B5_15, B5_14, B5_13, B5_12);
Z1_q_a[7]_PORT_A_address_reg = DFFE(Z1_q_a[7]_PORT_A_address, Z1_q_a[7]_clock_0, , , );
Z1_q_a[7]_PORT_B_address = BUS(B5_19, B5_18, B5_17, B5_16, B5_15, B5_14, B5_13, B5_12);
Z1_q_a[7]_PORT_B_address_reg = DFFE(Z1_q_a[7]_PORT_B_address, Z1_q_a[7]_clock_0, , , );
Z1_q_a[7]_PORT_A_write_enable = 70;
Z1_q_a[7]_PORT_A_write_enable_reg = DFFE(Z1_q_a[7]_PORT_A_write_enable, Z1_q_a[7]_clock_0, , , );
Z1_q_a[7]_clock_0 = CLK;
Z1_q_a[7]_PORT_A_data_out = MEMORY(Z1_q_a[7]_PORT_A_data_in_reg, , Z1_q_a[7]_PORT_A_address_reg, Z1_q_a[7]_PORT_B_address_reg, Z1_q_a[7]_PORT_A_write_enable_reg, , , , Z1_q_a[7]_clock_0, , , , , );
Z1_q_a[7]_PORT_A_data_out_reg = DFFE(Z1_q_a[7]_PORT_A_data_out, Z1_q_a[7]_clock_0, , , );
Z1_q_a[7] = Z1_q_a[7]_PORT_A_data_out_reg[0];


--S4L71 is 8cpu:92|busmux:49|lpm_mux:$00000|mux_afc:auto_generated|w_result97w~88
--operation mode is normal

S4L71 = S4L51 & (S4L61) # !S4L51 & (S4L61 & B9_12 # !S4L61 & (Z1_q_a[7]));


--S4L81 is 8cpu:92|busmux:49|lpm_mux:$00000|mux_afc:auto_generated|w_result97w~89
--operation mode is normal

S4L81 = S4L51 & (S4L71 & (kdata[8]) # !S4L71 & X1L82) # !S4L51 & (S4L71);


--S4L91 is 8cpu:92|busmux:49|lpm_mux:$00000|mux_afc:auto_generated|w_result97w~90
--operation mode is normal

S4L91 = H1_33 & B1_14 & B1_15;


--B9_13 is 8cpu:92|alu:62|74273b:11|13
--operation mode is normal

B9_13_lut_out = W3L4;
B9_13 = DFFEAS(B9_13_lut_out, M1_22, VCC, , , , , , );


--X1L52 is 8cpu:92|bi74670:67|74670c:32|121~11
--operation mode is normal

X1L52 = 69 & (68) # !69 & (68 & X1_66 # !68 & (X1_56));


--X1L62 is 8cpu:92|bi74670:67|74670c:32|121~12
--operation mode is normal

X1L62 = 69 & (X1L52 & (X1_75) # !X1L52 & X1_65) # !69 & (X1L52);


--Z1_q_a[6] is 8cpu:92|lpm_ram_dq0:inst|altsyncram:altsyncram_component|altsyncram_rs21:auto_generated|q_a[6]
--RAM Block Operation Mode: Single Port
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
Z1_q_a[6]_PORT_A_data_in = K3L51;
Z1_q_a[6]_PORT_A_data_in_reg = DFFE(Z1_q_a[6]_PORT_A_data_in, Z1_q_a[6]_clock_0, , , );
Z1_q_a[6]_PORT_A_address = BUS(B5_19, B5_18, B5_17, B5_16, B5_15, B5_14, B5_13, B5_12);
Z1_q_a[6]_PORT_A_address_reg = DFFE(Z1_q_a[6]_PORT_A_address, Z1_q_a[6]_clock_0, , , );
Z1_q_a[6]_PORT_B_address = BUS(B5_19, B5_18, B5_17, B5_16, B5_15, B5_14, B5_13, B5_12);
Z1_q_a[6]_PORT_B_address_reg = DFFE(Z1_q_a[6]_PORT_B_address, Z1_q_a[6]_clock_0, , , );
Z1_q_a[6]_PORT_A_write_enable = 70;
Z1_q_a[6]_PORT_A_write_enable_reg = DFFE(Z1_q_a[6]_PORT_A_write_enable, Z1_q_a[6]_clock_0, , , );
Z1_q_a[6]_clock_0 = CLK;
Z1_q_a[6]_PORT_A_data_out = MEMORY(Z1_q_a[6]_PORT_A_data_in_reg, , Z1_q_a[6]_PORT_A_address_reg, Z1_q_a[6]_PORT_B_address_reg, Z1_q_a[6]_PORT_A_write_enable_reg, , , , Z1_q_a[6]_clock_0, , , , , );
Z1_q_a[6]_PORT_A_data_out_reg = DFFE(Z1_q_a[6]_PORT_A_data_out, Z1_q_a[6]_clock_0, , , );
Z1_q_a[6] = Z1_q_a[6]_PORT_A_data_out_reg[0];


--S4L31 is 8cpu:92|busmux:49|lpm_mux:$00000|mux_afc:auto_generated|w_result85w~16
--operation mode is normal

S4L31 = S4L61 & (S4L51) # !S4L61 & (S4L51 & X1L62 # !S4L51 & (Z1_q_a[6]));


--S4L41 is 8cpu:92|busmux:49|lpm_mux:$00000|mux_afc:auto_generated|w_result85w~17
--operation mode is normal

S4L41 = S4L61 & (S4L31 & (kdata[7]) # !S4L31 & B9_13) # !S4L61 & (S4L31);


--K3L31 is 8cpu:92|pc:65|74161:9|f74161:sub|95~0
--operation mode is arithmetic

K3L31_carry_eqn = K3_85;
K3L31 = K3_99 $ (K3L7 & K3L31_carry_eqn);

--K3_95 is 8cpu:92|pc:65|74161:9|f74161:sub|95
--operation mode is arithmetic

K3_95 = CARRY(!K3_85 # !K3_99);


--X1L32 is 8cpu:92|bi74670:67|74670c:32|112~11
--operation mode is normal

X1L32 = 68 & (69) # !68 & (69 & X1_40 # !69 & (X1_51));


--X1L42 is 8cpu:92|bi74670:67|74670c:32|112~12
--operation mode is normal

X1L42 = 68 & (X1L32 & (X1_30) # !X1L32 & X1_39) # !68 & (X1L32);


--B9_14 is 8cpu:92|alu:62|74273b:11|14
--operation mode is normal

B9_14_lut_out = W3L6;
B9_14 = DFFEAS(B9_14_lut_out, M1_22, VCC, , , , , , );


--Z1_q_a[5] is 8cpu:92|lpm_ram_dq0:inst|altsyncram:altsyncram_component|altsyncram_rs21:auto_generated|q_a[5]
--RAM Block Operation Mode: Single Port
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
Z1_q_a[5]_PORT_A_data_in = K3L11;
Z1_q_a[5]_PORT_A_data_in_reg = DFFE(Z1_q_a[5]_PORT_A_data_in, Z1_q_a[5]_clock_0, , , );
Z1_q_a[5]_PORT_A_address = BUS(B5_19, B5_18, B5_17, B5_16, B5_15, B5_14, B5_13, B5_12);
Z1_q_a[5]_PORT_A_address_reg = DFFE(Z1_q_a[5]_PORT_A_address, Z1_q_a[5]_clock_0, , , );
Z1_q_a[5]_PORT_B_address = BUS(B5_19, B5_18, B5_17, B5_16, B5_15, B5_14, B5_13, B5_12);
Z1_q_a[5]_PORT_B_address_reg = DFFE(Z1_q_a[5]_PORT_B_address, Z1_q_a[5]_clock_0, , , );
Z1_q_a[5]_PORT_A_write_enable = 70;
Z1_q_a[5]_PORT_A_write_enable_reg = DFFE(Z1_q_a[5]_PORT_A_write_enable, Z1_q_a[5]_clock_0, , , );
Z1_q_a[5]_clock_0 = CLK;
Z1_q_a[5]_PORT_A_data_out = MEMORY(Z1_q_a[5]_PORT_A_data_in_reg, , Z1_q_a[5]_PORT_A_address_reg, Z1_q_a[5]_PORT_B_address_reg, Z1_q_a[5]_PORT_A_write_enable_reg, , , , Z1_q_a[5]_clock_0, , , , , );
Z1_q_a[5]_PORT_A_data_out_reg = DFFE(Z1_q_a[5]_PORT_A_data_out, Z1_q_a[5]_clock_0, , , );
Z1_q_a[5] = Z1_q_a[5]_PORT_A_data_out_reg[0];


--S4L11 is 8cpu:92|busmux:49|lpm_mux:$00000|mux_afc:auto_generated|w_result73w~16
--operation mode is normal

S4L11 = S4L51 & (S4L61) # !S4L51 & (S4L61 & B9_14 # !S4L61 & (Z1_q_a[5]));


--S4L21 is 8cpu:92|busmux:49|lpm_mux:$00000|mux_afc:auto_generated|w_result73w~17
--operation mode is normal

S4L21 = S4L51 & (S4L11 & (kdata[6]) # !S4L11 & X1L42) # !S4L51 & (S4L11);


--K3L9 is 8cpu:92|pc:65|74161:9|f74161:sub|85~0
--operation mode is arithmetic

K3L9_carry_eqn = K3_81;
K3L9 = K3_87 $ (K3L7 & !K3L9_carry_eqn);

--K3_85 is 8cpu:92|pc:65|74161:9|f74161:sub|85
--operation mode is arithmetic

K3_85 = CARRY(K3_87 & (!K3_81));


--B9_15 is 8cpu:92|alu:62|74273b:11|15
--operation mode is normal

B9_15_lut_out = W3L8;
B9_15 = DFFEAS(B9_15_lut_out, M1_22, VCC, , , , , , );


--X1L12 is 8cpu:92|bi74670:67|74670c:32|107~11
--operation mode is normal

X1L12 = 69 & (68) # !69 & (68 & X1_20 # !68 & (X1_5));


--X1L22 is 8cpu:92|bi74670:67|74670c:32|107~12
--operation mode is normal

X1L22 = 69 & (X1L12 & (X1_29) # !X1L12 & X1_19) # !69 & (X1L12);


--Z1_q_a[4] is 8cpu:92|lpm_ram_dq0:inst|altsyncram:altsyncram_component|altsyncram_rs21:auto_generated|q_a[4]
--RAM Block Operation Mode: Single Port
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
Z1_q_a[4]_PORT_A_data_in = K3L2;
Z1_q_a[4]_PORT_A_data_in_reg = DFFE(Z1_q_a[4]_PORT_A_data_in, Z1_q_a[4]_clock_0, , , );
Z1_q_a[4]_PORT_A_address = BUS(B5_19, B5_18, B5_17, B5_16, B5_15, B5_14, B5_13, B5_12);
Z1_q_a[4]_PORT_A_address_reg = DFFE(Z1_q_a[4]_PORT_A_address, Z1_q_a[4]_clock_0, , , );
Z1_q_a[4]_PORT_B_address = BUS(B5_19, B5_18, B5_17, B5_16, B5_15, B5_14, B5_13, B5_12);
Z1_q_a[4]_PORT_B_address_reg = DFFE(Z1_q_a[4]_PORT_B_address, Z1_q_a[4]_clock_0, , , );
Z1_q_a[4]_PORT_A_write_enable = 70;
Z1_q_a[4]_PORT_A_write_enable_reg = DFFE(Z1_q_a[4]_PORT_A_write_enable, Z1_q_a[4]_clock_0, , , );
Z1_q_a[4]_clock_0 = CLK;
Z1_q_a[4]_PORT_A_data_out = MEMORY(Z1_q_a[4]_PORT_A_data_in_reg, , Z1_q_a[4]_PORT_A_address_reg, Z1_q_a[4]_PORT_B_address_reg, Z1_q_a[4]_PORT_A_write_enable_reg, , , , Z1_q_a[4]_clock_0, , , , , );
Z1_q_a[4]_PORT_A_data_out_reg = DFFE(Z1_q_a[4]_PORT_A_data_out, Z1_q_a[4]_clock_0, , , );
Z1_q_a[4] = Z1_q_a[4]_PORT_A_data_out_reg[0];


--S4L9 is 8cpu:92|busmux:49|lpm_mux:$00000|mux_afc:auto_generated|w_result61w~16
--operation mode is normal

S4L9 = S4L61 & (S4L51) # !S4L61 & (S4L51 & X1L22 # !S4L51 & (Z1_q_a[4]));


--S4L01 is 8cpu:92|busmux:49|lpm_mux:$00000|mux_afc:auto_generated|w_result61w~17
--operation mode is normal

S4L01 = S4L61 & (S4L9 & (kdata[5]) # !S4L9 & B9_15) # !S4L61 & (S4L9);


--K3L4 is 8cpu:92|pc:65|74161:9|f74161:sub|81~0
--operation mode is arithmetic

K3L4_carry_eqn = K3L6;
K3L4 = K3_9 $ (K3L4_carry_eqn);

--K3_81 is 8cpu:92|pc:65|74161:9|f74161:sub|81
--operation mode is arithmetic

K3_81 = CARRY(!K3L6 # !K3_9);


--X2L32 is 8cpu:92|bi74670:67|74670c:34|126~11
--operation mode is normal

X2L32 = 68 & (69) # !68 & (69 & X2_86 # !69 & (X2_95));


--X2L42 is 8cpu:92|bi74670:67|74670c:34|126~12
--operation mode is normal

X2L42 = 68 & (X2L32 & (X2_76) # !X2L32 & X2_85) # !68 & (X2L32);


--B9_16 is 8cpu:92|alu:62|74273b:11|16
--operation mode is normal

B9_16_lut_out = W3L01;
B9_16 = DFFEAS(B9_16_lut_out, M1_22, VCC, , , , , , );


--Z1_q_a[3] is 8cpu:92|lpm_ram_dq0:inst|altsyncram:altsyncram_component|altsyncram_rs21:auto_generated|q_a[3]
--RAM Block Operation Mode: Single Port
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
Z1_q_a[3]_PORT_A_data_in = K2L71;
Z1_q_a[3]_PORT_A_data_in_reg = DFFE(Z1_q_a[3]_PORT_A_data_in, Z1_q_a[3]_clock_0, , , );
Z1_q_a[3]_PORT_A_address = BUS(B5_19, B5_18, B5_17, B5_16, B5_15, B5_14, B5_13, B5_12);
Z1_q_a[3]_PORT_A_address_reg = DFFE(Z1_q_a[3]_PORT_A_address, Z1_q_a[3]_clock_0, , , );
Z1_q_a[3]_PORT_B_address = BUS(B5_19, B5_18, B5_17, B5_16, B5_15, B5_14, B5_13, B5_12);
Z1_q_a[3]_PORT_B_address_reg = DFFE(Z1_q_a[3]_PORT_B_address, Z1_q_a[3]_clock_0, , , );
Z1_q_a[3]_PORT_A_write_enable = 70;
Z1_q_a[3]_PORT_A_write_enable_reg = DFFE(Z1_q_a[3]_PORT_A_write_enable, Z1_q_a[3]_clock_0, , , );
Z1_q_a[3]_clock_0 = CLK;
Z1_q_a[3]_PORT_A_data_out = MEMORY(Z1_q_a[3]_PORT_A_data_in_reg, , Z1_q_a[3]_PORT_A_address_reg, Z1_q_a[3]_PORT_B_address_reg, Z1_q_a[3]_PORT_A_write_enable_reg, , , , Z1_q_a[3]_clock_0, , , , , );
Z1_q_a[3]_PORT_A_data_out_reg = DFFE(Z1_q_a[3]_PORT_A_data_out, Z1_q_a[3]_clock_0, , , );
Z1_q_a[3] = Z1_q_a[3]_PORT_A_data_out_reg[0];


--S4L7 is 8cpu:92|busmux:49|lpm_mux:$00000|mux_afc:auto_generated|w_result49w~16
--operation mode is normal

S4L7 = S4L51 & (S4L61) # !S4L51 & (S4L61 & B9_16 # !S4L61 & (Z1_q_a[3]));


--S4L8 is 8cpu:92|busmux:49|lpm_mux:$00000|mux_afc:auto_generated|w_result49w~17
--operation mode is normal

S4L8 = S4L51 & (S4L7 & (kdata[4]) # !S4L7 & X2L42) # !S4L51 & (S4L7);


--K2L51 is 8cpu:92|pc:65|74161:8|f74161:sub|105~0
--operation mode is arithmetic

K2L51_carry_eqn = K2_95;
K2L51 = K2_110 $ (K2L51_carry_eqn);

--K2_105 is 8cpu:92|pc:65|74161:8|f74161:sub|105
--operation mode is arithmetic

K2_105 = CARRY(!K2_95 # !K2_110);


--B9_17 is 8cpu:92|alu:62|74273b:11|17
--operation mode is normal

B9_17_lut_out = W3L21;
B9_17 = DFFEAS(B9_17_lut_out, M1_22, VCC, , , , , , );


--X2L12 is 8cpu:92|bi74670:67|74670c:34|121~11
--operation mode is normal

X2L12 = 69 & (68) # !69 & (68 & X2_66 # !68 & (X2_56));


--X2L22 is 8cpu:92|bi74670:67|74670c:34|121~12
--operation mode is normal

X2L22 = 69 & (X2L12 & (X2_75) # !X2L12 & X2_65) # !69 & (X2L12);


--Z1_q_a[2] is 8cpu:92|lpm_ram_dq0:inst|altsyncram:altsyncram_component|altsyncram_rs21:auto_generated|q_a[2]
--RAM Block Operation Mode: Single Port
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
Z1_q_a[2]_PORT_A_data_in = K2L31;
Z1_q_a[2]_PORT_A_data_in_reg = DFFE(Z1_q_a[2]_PORT_A_data_in, Z1_q_a[2]_clock_0, , , );
Z1_q_a[2]_PORT_A_address = BUS(B5_19, B5_18, B5_17, B5_16, B5_15, B5_14, B5_13, B5_12);
Z1_q_a[2]_PORT_A_address_reg = DFFE(Z1_q_a[2]_PORT_A_address, Z1_q_a[2]_clock_0, , , );
Z1_q_a[2]_PORT_B_address = BUS(B5_19, B5_18, B5_17, B5_16, B5_15, B5_14, B5_13, B5_12);
Z1_q_a[2]_PORT_B_address_reg = DFFE(Z1_q_a[2]_PORT_B_address, Z1_q_a[2]_clock_0, , , );
Z1_q_a[2]_PORT_A_write_enable = 70;
Z1_q_a[2]_PORT_A_write_enable_reg = DFFE(Z1_q_a[2]_PORT_A_write_enable, Z1_q_a[2]_clock_0, , , );
Z1_q_a[2]_clock_0 = CLK;
Z1_q_a[2]_PORT_A_data_out = MEMORY(Z1_q_a[2]_PORT_A_data_in_reg, , Z1_q_a[2]_PORT_A_address_reg, Z1_q_a[2]_PORT_B_address_reg, Z1_q_a[2]_PORT_A_write_enable_reg, , , , Z1_q_a[2]_clock_0, , , , , );
Z1_q_a[2]_PORT_A_data_out_reg = DFFE(Z1_q_a[2]_PORT_A_data_out, Z1_q_a[2]_clock_0, , , );
Z1_q_a[2] = Z1_q_a[2]_PORT_A_data_out_reg[0];


--S4L5 is 8cpu:92|busmux:49|lpm_mux:$00000|mux_afc:auto_generated|w_result37w~16
--operation mode is normal

S4L5 = S4L61 & (S4L51) # !S4L61 & (S4L51 & X2L22 # !S4L51 & (Z1_q_a[2]));


--S4L6 is 8cpu:92|busmux:49|lpm_mux:$00000|mux_afc:auto_generated|w_result37w~17
--operation mode is normal

S4L6 = S4L61 & (S4L5 & (kdata[3]) # !S4L5 & B9_17) # !S4L61 & (S4L5);


--K2L11 is 8cpu:92|pc:65|74161:8|f74161:sub|95~0
--operation mode is arithmetic

K2L11_carry_eqn = K2_85;
K2L11 = K2_99 $ (!K2L11_carry_eqn);

--K2_95 is 8cpu:92|pc:65|74161:8|f74161:sub|95
--operation mode is arithmetic

K2_95 = CARRY(K2_99 & (!K2_85));


--X2L91 is 8cpu:92|bi74670:67|74670c:34|112~11
--operation mode is normal

X2L91 = 68 & (69) # !68 & (69 & X2_40 # !69 & (X2_51));


--X2L02 is 8cpu:92|bi74670:67|74670c:34|112~12
--operation mode is normal

X2L02 = 68 & (X2L91 & (X2_30) # !X2L91 & X2_39) # !68 & (X2L91);


--B9_18 is 8cpu:92|alu:62|74273b:11|18
--operation mode is normal

B9_18_lut_out = W3L41;
B9_18 = DFFEAS(B9_18_lut_out, M1_22, VCC, , , , , , );


--Z1_q_a[1] is 8cpu:92|lpm_ram_dq0:inst|altsyncram:altsyncram_component|altsyncram_rs21:auto_generated|q_a[1]
--RAM Block Operation Mode: Single Port
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered