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📄 mycpu.map.eqn

📁 Quartus II 5.0下写的一个单总线架构的CPU设计
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--Port A Input: Registered, Port A Output: Registered
BB1_q_a[13]_PORT_A_address = BUS(K1_9, K1_87, K1_99, K1_110, B3_15, B3_14, 24, 25);
BB1_q_a[13]_PORT_A_address_reg = DFFE(BB1_q_a[13]_PORT_A_address, BB1_q_a[13]_clock_0, , , );
BB1_q_a[13]_clock_0 = CLK;
BB1_q_a[13]_PORT_A_data_out = MEMORY(, , BB1_q_a[13]_PORT_A_address_reg, , , , , , BB1_q_a[13]_clock_0, , , , , );
BB1_q_a[13]_PORT_A_data_out_reg = DFFE(BB1_q_a[13]_PORT_A_data_out, BB1_q_a[13]_clock_0, , , );
BB1_q_a[13] = BB1_q_a[13]_PORT_A_data_out_reg[0];


--39 is 39
--operation mode is normal

39 = H1_28 & CLK;


--BB1_q_a[1] is lpm_rom6:inst2|altsyncram:altsyncram_component|altsyncram_3mp:auto_generated|q_a[1]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 24
--Port A Input: Registered, Port A Output: Registered
BB1_q_a[1]_PORT_A_address = BUS(K1_9, K1_87, K1_99, K1_110, B3_15, B3_14, 24, 25);
BB1_q_a[1]_PORT_A_address_reg = DFFE(BB1_q_a[1]_PORT_A_address, BB1_q_a[1]_clock_0, , , );
BB1_q_a[1]_clock_0 = CLK;
BB1_q_a[1]_PORT_A_data_out = MEMORY(, , BB1_q_a[1]_PORT_A_address_reg, , , , , , BB1_q_a[1]_clock_0, , , , , );
BB1_q_a[1]_PORT_A_data_out_reg = DFFE(BB1_q_a[1]_PORT_A_data_out, BB1_q_a[1]_clock_0, , , );
BB1_q_a[1] = BB1_q_a[1]_PORT_A_data_out_reg[0];


--K3L81 is 8cpu:92|pc:65|74161:9|f74161:sub|110~COMBOUT
--operation mode is normal

K3L81 = S4L91 & (K3_110) # !S4L91 & S4L81;

--K3_110 is 8cpu:92|pc:65|74161:9|f74161:sub|110
--operation mode is normal

K3_110 = DFFEAS(K3L81, G1L3, CLRN, , , K3_107, , , 61);


--G1_12 is 8cpu:92|12
--operation mode is normal

G1_12 = H1_33 & B1_19 & CLK;


--K3L51 is 8cpu:92|pc:65|74161:9|f74161:sub|99~COMBOUT
--operation mode is normal

K3L51 = S4L91 & (K3_99) # !S4L91 & S4L41;

--K3_99 is 8cpu:92|pc:65|74161:9|f74161:sub|99
--operation mode is normal

K3_99 = DFFEAS(K3L51, G1L3, CLRN, , , K3L31, , , 61);


--K3L11 is 8cpu:92|pc:65|74161:9|f74161:sub|87~COMBOUT
--operation mode is normal

K3L11 = S4L91 & (K3_87) # !S4L91 & S4L21;

--K3_87 is 8cpu:92|pc:65|74161:9|f74161:sub|87
--operation mode is normal

K3_87 = DFFEAS(K3L11, G1L3, CLRN, , , K3L9, , , 61);


--K3L2 is 8cpu:92|pc:65|74161:9|f74161:sub|9~COMBOUT
--operation mode is normal

K3L2 = S4L91 & (K3_9) # !S4L91 & S4L01;

--K3_9 is 8cpu:92|pc:65|74161:9|f74161:sub|9
--operation mode is normal

K3_9 = DFFEAS(K3L2, G1L3, CLRN, , , K3L4, , , 61);


--K2L71 is 8cpu:92|pc:65|74161:8|f74161:sub|110~COMBOUT
--operation mode is normal

K2L71 = S4L91 & (K2_110) # !S4L91 & S4L8;

--K2_110 is 8cpu:92|pc:65|74161:8|f74161:sub|110
--operation mode is normal

K2_110 = DFFEAS(K2L71, G1L3, CLRN, , , K2L51, , , 61);


--K2L31 is 8cpu:92|pc:65|74161:8|f74161:sub|99~COMBOUT
--operation mode is normal

K2L31 = S4L91 & (K2_99) # !S4L91 & S4L6;

--K2_99 is 8cpu:92|pc:65|74161:8|f74161:sub|99
--operation mode is normal

K2_99 = DFFEAS(K2L31, G1L3, CLRN, , , K2L11, , , 61);


--K2L9 is 8cpu:92|pc:65|74161:8|f74161:sub|87~COMBOUT
--operation mode is normal

K2L9 = S4L91 & (K2_87) # !S4L91 & S4L4;

--K2_87 is 8cpu:92|pc:65|74161:8|f74161:sub|87
--operation mode is normal

K2_87 = DFFEAS(K2L9, G1L3, CLRN, , , K2L7, , , 61);


--K2L2 is 8cpu:92|pc:65|74161:8|f74161:sub|9~COMBOUT
--operation mode is normal

K2L2 = S4L91 & (K2L4) # !S4L91 & S4L2;

--K2_9 is 8cpu:92|pc:65|74161:8|f74161:sub|9
--operation mode is normal

K2_9 = DFFEAS(K2L2, G1L3, CLRN, , , K2L5, , , 61);


--BB1_q_a[15] is lpm_rom6:inst2|altsyncram:altsyncram_component|altsyncram_3mp:auto_generated|q_a[15]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 24
--Port A Input: Registered, Port A Output: Registered
BB1_q_a[15]_PORT_A_address = BUS(K1_9, K1_87, K1_99, K1_110, B3_15, B3_14, 24, 25);
BB1_q_a[15]_PORT_A_address_reg = DFFE(BB1_q_a[15]_PORT_A_address, BB1_q_a[15]_clock_0, , , );
BB1_q_a[15]_clock_0 = CLK;
BB1_q_a[15]_PORT_A_data_out = MEMORY(, , BB1_q_a[15]_PORT_A_address_reg, , , , , , BB1_q_a[15]_clock_0, , , , , );
BB1_q_a[15]_PORT_A_data_out_reg = DFFE(BB1_q_a[15]_PORT_A_data_out, BB1_q_a[15]_clock_0, , , );
BB1_q_a[15] = BB1_q_a[15]_PORT_A_data_out_reg[0];


--BB1_q_a[14] is lpm_rom6:inst2|altsyncram:altsyncram_component|altsyncram_3mp:auto_generated|q_a[14]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 24
--Port A Input: Registered, Port A Output: Registered
BB1_q_a[14]_PORT_A_address = BUS(K1_9, K1_87, K1_99, K1_110, B3_15, B3_14, 24, 25);
BB1_q_a[14]_PORT_A_address_reg = DFFE(BB1_q_a[14]_PORT_A_address, BB1_q_a[14]_clock_0, , , );
BB1_q_a[14]_clock_0 = CLK;
BB1_q_a[14]_PORT_A_data_out = MEMORY(, , BB1_q_a[14]_PORT_A_address_reg, , , , , , BB1_q_a[14]_clock_0, , , , , );
BB1_q_a[14]_PORT_A_data_out_reg = DFFE(BB1_q_a[14]_PORT_A_data_out, BB1_q_a[14]_clock_0, , , );
BB1_q_a[14] = BB1_q_a[14]_PORT_A_data_out_reg[0];


--BB1_q_a[12] is lpm_rom6:inst2|altsyncram:altsyncram_component|altsyncram_3mp:auto_generated|q_a[12]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 24
--Port A Input: Registered, Port A Output: Registered
BB1_q_a[12]_PORT_A_address = BUS(K1_9, K1_87, K1_99, K1_110, B3_15, B3_14, 24, 25);
BB1_q_a[12]_PORT_A_address_reg = DFFE(BB1_q_a[12]_PORT_A_address, BB1_q_a[12]_clock_0, , , );
BB1_q_a[12]_clock_0 = CLK;
BB1_q_a[12]_PORT_A_data_out = MEMORY(, , BB1_q_a[12]_PORT_A_address_reg, , , , , , BB1_q_a[12]_clock_0, , , , , );
BB1_q_a[12]_PORT_A_data_out_reg = DFFE(BB1_q_a[12]_PORT_A_data_out, BB1_q_a[12]_clock_0, , , );
BB1_q_a[12] = BB1_q_a[12]_PORT_A_data_out_reg[0];


--BB1_q_a[11] is lpm_rom6:inst2|altsyncram:altsyncram_component|altsyncram_3mp:auto_generated|q_a[11]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 24
--Port A Input: Registered, Port A Output: Registered
BB1_q_a[11]_PORT_A_address = BUS(K1_9, K1_87, K1_99, K1_110, B3_15, B3_14, 24, 25);
BB1_q_a[11]_PORT_A_address_reg = DFFE(BB1_q_a[11]_PORT_A_address, BB1_q_a[11]_clock_0, , , );
BB1_q_a[11]_clock_0 = CLK;
BB1_q_a[11]_PORT_A_data_out = MEMORY(, , BB1_q_a[11]_PORT_A_address_reg, , , , , , BB1_q_a[11]_clock_0, , , , , );
BB1_q_a[11]_PORT_A_data_out_reg = DFFE(BB1_q_a[11]_PORT_A_data_out, BB1_q_a[11]_clock_0, , , );
BB1_q_a[11] = BB1_q_a[11]_PORT_A_data_out_reg[0];


--BB1_q_a[10] is lpm_rom6:inst2|altsyncram:altsyncram_component|altsyncram_3mp:auto_generated|q_a[10]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 24
--Port A Input: Registered, Port A Output: Registered
BB1_q_a[10]_PORT_A_address = BUS(K1_9, K1_87, K1_99, K1_110, B3_15, B3_14, 24, 25);
BB1_q_a[10]_PORT_A_address_reg = DFFE(BB1_q_a[10]_PORT_A_address, BB1_q_a[10]_clock_0, , , );
BB1_q_a[10]_clock_0 = CLK;
BB1_q_a[10]_PORT_A_data_out = MEMORY(, , BB1_q_a[10]_PORT_A_address_reg, , , , , , BB1_q_a[10]_clock_0, , , , , );
BB1_q_a[10]_PORT_A_data_out_reg = DFFE(BB1_q_a[10]_PORT_A_data_out, BB1_q_a[10]_clock_0, , , );
BB1_q_a[10] = BB1_q_a[10]_PORT_A_data_out_reg[0];


--BB1_q_a[9] is lpm_rom6:inst2|altsyncram:altsyncram_component|altsyncram_3mp:auto_generated|q_a[9]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 24
--Port A Input: Registered, Port A Output: Registered
BB1_q_a[9]_PORT_A_address = BUS(K1_9, K1_87, K1_99, K1_110, B3_15, B3_14, 24, 25);
BB1_q_a[9]_PORT_A_address_reg = DFFE(BB1_q_a[9]_PORT_A_address, BB1_q_a[9]_clock_0, , , );
BB1_q_a[9]_clock_0 = CLK;
BB1_q_a[9]_PORT_A_data_out = MEMORY(, , BB1_q_a[9]_PORT_A_address_reg, , , , , , BB1_q_a[9]_clock_0, , , , , );
BB1_q_a[9]_PORT_A_data_out_reg = DFFE(BB1_q_a[9]_PORT_A_data_out, BB1_q_a[9]_clock_0, , , );
BB1_q_a[9] = BB1_q_a[9]_PORT_A_data_out_reg[0];


--BB1_q_a[8] is lpm_rom6:inst2|altsyncram:altsyncram_component|altsyncram_3mp:auto_generated|q_a[8]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 24
--Port A Input: Registered, Port A Output: Registered
BB1_q_a[8]_PORT_A_address = BUS(K1_9, K1_87, K1_99, K1_110, B3_15, B3_14, 24, 25);
BB1_q_a[8]_PORT_A_address_reg = DFFE(BB1_q_a[8]_PORT_A_address, BB1_q_a[8]_clock_0, , , );
BB1_q_a[8]_clock_0 = CLK;
BB1_q_a[8]_PORT_A_data_out = MEMORY(, , BB1_q_a[8]_PORT_A_address_reg, , , , , , BB1_q_a[8]_clock_0, , , , , );
BB1_q_a[8]_PORT_A_data_out_reg = DFFE(BB1_q_a[8]_PORT_A_data_out, BB1_q_a[8]_clock_0, , , );
BB1_q_a[8] = BB1_q_a[8]_PORT_A_data_out_reg[0];


--BB1_q_a[7] is lpm_rom6:inst2|altsyncram:altsyncram_component|altsyncram_3mp:auto_generated|q_a[7]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 24
--Port A Input: Registered, Port A Output: Registered
BB1_q_a[7]_PORT_A_address = BUS(K1_9, K1_87, K1_99, K1_110, B3_15, B3_14, 24, 25);
BB1_q_a[7]_PORT_A_address_reg = DFFE(BB1_q_a[7]_PORT_A_address, BB1_q_a[7]_clock_0, , , );
BB1_q_a[7]_clock_0 = CLK;
BB1_q_a[7]_PORT_A_data_out = MEMORY(, , BB1_q_a[7]_PORT_A_address_reg, , , , , , BB1_q_a[7]_clock_0, , , , , );
BB1_q_a[7]_PORT_A_data_out_reg = DFFE(BB1_q_a[7]_PORT_A_data_out, BB1_q_a[7]_clock_0, , , );
BB1_q_a[7] = BB1_q_a[7]_PORT_A_data_out_reg[0];


--BB1_q_a[6] is lpm_rom6:inst2|altsyncram:altsyncram_component|altsyncram_3mp:auto_generated|q_a[6]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 24
--Port A Input: Registered, Port A Output: Registered
BB1_q_a[6]_PORT_A_address = BUS(K1_9, K1_87, K1_99, K1_110, B3_15, B3_14, 24, 25);
BB1_q_a[6]_PORT_A_address_reg = DFFE(BB1_q_a[6]_PORT_A_address, BB1_q_a[6]_clock_0, , , );
BB1_q_a[6]_clock_0 = CLK;
BB1_q_a[6]_PORT_A_data_out = MEMORY(, , BB1_q_a[6]_PORT_A_address_reg, , , , , , BB1_q_a[6]_clock_0, , , , , );
BB1_q_a[6]_PORT_A_data_out_reg = DFFE(BB1_q_a[6]_PORT_A_data_out, BB1_q_a[6]_clock_0, , , );
BB1_q_a[6] = BB1_q_a[6]_PORT_A_data_out_reg[0];


--BB1_q_a[5] is lpm_rom6:inst2|altsyncram:altsyncram_component|altsyncram_3mp:auto_generated|q_a[5]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 24
--Port A Input: Registered, Port A Output: Registered
BB1_q_a[5]_PORT_A_address = BUS(K1_9, K1_87, K1_99, K1_110, B3_15, B3_14, 24, 25);
BB1_q_a[5]_PORT_A_address_reg = DFFE(BB1_q_a[5]_PORT_A_address, BB1_q_a[5]_clock_0, , , );
BB1_q_a[5]_clock_0 = CLK;
BB1_q_a[5]_PORT_A_data_out = MEMORY(, , BB1_q_a[5]_PORT_A_address_reg, , , , , , BB1_q_a[5]_clock_0, , , , , );
BB1_q_a[5]_PORT_A_data_out_reg = DFFE(BB1_q_a[5]_PORT_A_data_out, BB1_q_a[5]_clock_0, , , );
BB1_q_a[5] = BB1_q_a[5]_PORT_A_data_out_reg[0];


--BB1_q_a[4] is lpm_rom6:inst2|altsyncram:altsyncram_component|altsyncram_3mp:auto_generated|q_a[4]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 24
--Port A Input: Registered, Port A Output: Registered
BB1_q_a[4]_PORT_A_address = BUS(K1_9, K1_87, K1_99, K1_110, B3_15, B3_14, 24, 25);
BB1_q_a[4]_PORT_A_address_reg = DFFE(BB1_q_a[4]_PORT_A_address, BB1_q_a[4]_clock_0, , , );
BB1_q_a[4]_clock_0 = CLK;
BB1_q_a[4]_PORT_A_data_out = MEMORY(, , BB1_q_a[4]_PORT_A_address_reg, , , , , , BB1_q_a[4]_clock_0, , , , , );
BB1_q_a[4]_PORT_A_data_out_reg = DFFE(BB1_q_a[4]_PORT_A_data_out, BB1_q_a[4]_clock_0, , , );
BB1_q_a[4] = BB1_q_a[4]_PORT_A_data_out_reg[0];


--BB1_q_a[3] is lpm_rom6:inst2|altsyncram:altsyncram_component|altsyncram_3mp:auto_generated|q_a[3]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 24
--Port A Input: Registered, Port A Output: Registered
BB1_q_a[3]_PORT_A_address = BUS(K1_9, K1_87, K1_99, K1_110, B3_15, B3_14, 24, 25);
BB1_q_a[3]_PORT_A_address_reg = DFFE(BB1_q_a[3]_PORT_A_address, BB1_q_a[3]_clock_0, , , );
BB1_q_a[3]_clock_0 = CLK;
BB1_q_a[3]_PORT_A_data_out = MEMORY(, , BB1_q_a[3]_PORT_A_address_reg, , , , , , BB1_q_a[3]_clock_0, , , , , );
BB1_q_a[3]_PORT_A_data_out_reg = DFFE(BB1_q_a[3]_PORT_A_data_out, BB1_q_a[3]_clock_0, , , );
BB1_q_a[3] = BB1_q_a[3]_PORT_A_data_out_reg[0];


--BB1_q_a[2] is lpm_rom6:inst2|altsyncram:altsyncram_component|altsyncram_3mp:auto_generated|q_a[2]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 24
--Port A Input: Registered, Port A Output: Registered
BB1_q_a[2]_PORT_A_address = BUS(K1_9, K1_87, K1_99, K1_110, B3_15, B3_14, 24, 25);
BB1_q_a[2]_PORT_A_address_reg = DFFE(BB1_q_a[2]_PORT_A_address, BB1_q_a[2]_clock_0, , , );
BB1_q_a[2]_clock_0 = CLK;
BB1_q_a[2]_PORT_A_data_out = MEMORY(, , BB1_q_a[2]_PORT_A_address_reg, , , , , , BB1_q_a[2]_clock_0, , , , , );
BB1_q_a[2]_PORT_A_data_out_reg = DFFE(BB1_q_a[2]_PORT_A_data_out, BB1_q_a[2]_clock_0, , , );
BB1_q_a[2] = BB1_q_a[2]_PORT_A_data_out_reg[0];


--BB1_q_a[0] is lpm_rom6:inst2|altsyncram:altsyncram_component|altsyncram_3mp:auto_generated|q_a[0]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 24
--Port A Input: Registered, Port A Output: Registered
BB1_q_a[0]_PORT_A_address = BUS(K1_9, K1_87, K1_99, K1_110, B3_15, B3_14, 24, 25);
BB1_q_a[0]_PORT_A_address_reg = DFFE(BB1_q_a[0]_PORT_A_address, BB1_q_a[0]_clock_0, , , );
BB1_q_a[0]_clock_0 = CLK;
BB1_q_a[0]_PORT_A_data_out = MEMORY(, , BB1_q_a[0]_PORT_A_address_reg, , , , , , BB1_q_a[0]_clock_0, , , , , );
BB1_q_a[0]_PORT_A_data_out_reg = DFFE(BB1_q_a[0]_PORT_A_data_out, BB1_q_a[0]_clock_0, , , );
BB1_q_a[0] = BB1_q_a[0]_PORT_A_data_out_reg[0];


--K1_9 is 74161:12|f74161:sub|9
--operation mode is arithmetic

K1_9_lut_out = !K1_9;
K1_9 = DFFEAS(K1_9_lut_out, 17, !97, , , , , , );

--K1_81 is 74161:12|f74161:sub|81
--operation mode is arithmetic

K1_81 = CARRY(K1_9);


--K1_87 is 74161:12|f74161:sub|87
--operation mode is arithmetic

K1_87_carry_eqn = K1_81;
K1_87_lut_out = K1_87 $ (K1_87_carry_eqn);
K1_87 = DFFEAS(K1_87_lut_out, 17, !97, , , , , , );

--K1_85 is 74161:12|f74161:sub|85
--operation mode is arithmetic

K1_85 = CARRY(!K1_81 # !K1_87);


--K1_99 is 74161:12|f74161:sub|99
--operation mode is arithmetic

K1_99_carry_eqn = K1_85;
K1_99_lut_out = K1_99 $ (!K1_99_carry_eqn);
K1_99 = DFFEAS(K1_99_lut_out, 17, !97, , , , , , );

--K1_95 is 74161:12|f74161:sub|95
--operation mode is arithmetic

K1_95 = CARRY(K1_99 & (!K1_85));


--K1_110 is 74161:12|f74161:sub|110
--operation mode is normal

K1_110_carry_eqn = K1_95;
K1_110_lut_out = K1_110_carry_eqn $ K1_110;
K1_110 = DFFEAS(K1_110_lut_out, 17, !97, , , , , , );


--B3_15 is 74273b:10|15
--operation mode is normal

B3_15_lut_out = K3L2;
B3_15 = DFFEAS(B3_15_lut_out, 19, !76, , , , , , );


--B3_14 is 74273b:10|14
--operation mode is normal

B3_14_lut_out = K3L11;
B3_14 = DFFEAS(B3_14_lut_out, 19, !76, , , , , , );


--B3_13 is 74273b:10|13
--operation mode is normal

B3_13_lut_out = K3L51;
B3_13 = DFFEAS(B3_13_lut_out, 19, !76, , , , , , );


--24 is 24
--operation mode is normal

24 = B3_13 # K2;


--B3_12 is 74273b:10|12
--operation mode is normal

B3_12_lut_out = K3L81;
B3_12 = DFFEAS(B3_12_lut_out, 19, !76, , , , , , );


--25 is 25
--operation mode is normal

25 = B3_12 # K1;


--B8_12 is 8cpu:92|alu:62|74273b:5|12
--operation mode is normal

B8_12_lut_out = K3L81;
B8_12 = DFFEAS(B8_12_lut_out, M1_21, VCC, , , , , , );


--B7_12 is 8cpu:92|alu:62|74273b:4|12
--operation mode is normal

B7_12_lut_out = K3L81;
B7_12 = DFFEAS(B7_12_lut_out, M1_18, VCC, , , , , , );


--W3L4 is 8cpu:92|alu:62|lpm_add_sub:1|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~161
--operation mode is arithmetic

W3L4_carry_eqn = W3L7;
W3L4 = B8_13 $ B7_13 $ !W3L4_carry_eqn;

--W3L5 is 8cpu:92|alu:62|lpm_add_sub:1|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~163
--operation mode is arithmetic

W3L5 = CARRY(B8_13 & (B7_13 # !W3L7) # !B8_13 & B7_13 & !W3L7);


--A1L21 is 91~40
--operation mode is normal

A1L21 = B4_18 & K3;


--A1L31 is 91~41
--operation mode is normal

A1L31 = H1_35 & (B4_19 # A1L21) # !CLRN;


--61 is 61
--operation mode is normal

61 = !B2_19 # !H1_33;


--G1L3 is 8cpu:92|59~44
--operation mode is normal

G1L3 = CLK & (H1_35 & B2_13 # !61);


--B3_19 is 74273b:10|19
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