mycpu.map.eqn

Quartus II 5.0下写的一个单总线架构的CPU设计

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--W3L1 is 8cpu:92|alu:62|lpm_add_sub:1|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~151
--operation mode is normal

W3L1_carry_eqn = W3L3;
W3L1 = !W3L1_carry_eqn;


--AB1_9 is sequence:103|74393b:25|9
--operation mode is normal

AB1_9_lut_out = !AB1_9;
AB1_9 = DFFEAS(AB1_9_lut_out, !CLK, F1_11, , AB1_11, , , , );


--AB1_3 is sequence:103|74393b:25|3
--operation mode is normal

AB1_3_lut_out = !AB1_3;
AB1_3 = DFFEAS(AB1_3_lut_out, !CLK, F1_11, , AB1_1, , , , );


--AB1_1 is sequence:103|74393b:25|1
--operation mode is normal

AB1_1_lut_out = !AB1_1;
AB1_1 = DFFEAS(AB1_1_lut_out, !CLK, F1_11, , , , , , );


--AB1_5 is sequence:103|74393b:25|5
--operation mode is normal

AB1_5_lut_out = !AB1_5;
AB1_5 = DFFEAS(AB1_5_lut_out, !CLK, F1_11, , AB1L4, , , , );


--H1_33 is sequence:103|33
--operation mode is normal

H1_33 = AB1_9 & AB1_3 & !AB1_1 & !AB1_5;


--H1_28 is sequence:103|28
--operation mode is normal

H1_28 = AB1_3 & !AB1_9 & !AB1_1 & !AB1_5;


--H1_35 is sequence:103|35
--operation mode is normal

H1_35 = AB1_9 & AB1_5 & !AB1_1 & !AB1_3;


--B2_14 is 74273b:3|14
--operation mode is normal

B2_14_lut_out = BB1_q_a[13];
B2_14 = DFFEAS(B2_14_lut_out, 39, CLRN, , , , , , );


--B4_18 is 74273b:21|18
--operation mode is normal

B4_18_lut_out = BB1_q_a[1];
B4_18 = DFFEAS(B4_18_lut_out, 39, CLRN, , , , , , );


--97 is 97
--operation mode is normal

97 = H1_35 & (B2_14 # B4_18) # !CLRN;


--H1_37 is sequence:103|37
--operation mode is normal

H1_37 = AB1_5 & !AB1_9 & !AB1_1 & !AB1_3;


--B6_12 is 8cpu:92|74273b:7|12
--operation mode is normal

B6_12_lut_out = K3L81;
B6_12 = DFFEAS(B6_12_lut_out, G1_12, VCC, , , , , , );


--B6_13 is 8cpu:92|74273b:7|13
--operation mode is normal

B6_13_lut_out = K3L51;
B6_13 = DFFEAS(B6_13_lut_out, G1_12, VCC, , , , , , );


--B6_14 is 8cpu:92|74273b:7|14
--operation mode is normal

B6_14_lut_out = K3L11;
B6_14 = DFFEAS(B6_14_lut_out, G1_12, VCC, , , , , , );


--B6_15 is 8cpu:92|74273b:7|15
--operation mode is normal

B6_15_lut_out = K3L2;
B6_15 = DFFEAS(B6_15_lut_out, G1_12, VCC, , , , , , );


--B6_16 is 8cpu:92|74273b:7|16
--operation mode is normal

B6_16_lut_out = K2L71;
B6_16 = DFFEAS(B6_16_lut_out, G1_12, VCC, , , , , , );


--B6_17 is 8cpu:92|74273b:7|17
--operation mode is normal

B6_17_lut_out = K2L31;
B6_17 = DFFEAS(B6_17_lut_out, G1_12, VCC, , , , , , );


--B6_18 is 8cpu:92|74273b:7|18
--operation mode is normal

B6_18_lut_out = K2L9;
B6_18 = DFFEAS(B6_18_lut_out, G1_12, VCC, , , , , , );


--B6_19 is 8cpu:92|74273b:7|19
--operation mode is normal

B6_19_lut_out = K2L2;
B6_19 = DFFEAS(B6_19_lut_out, G1_12, VCC, , , , , , );


--B1_12 is 74273b:2|12
--operation mode is normal

B1_12_lut_out = BB1_q_a[23];
B1_12 = DFFEAS(B1_12_lut_out, 39, CLRN, , , , , , );


--B1_13 is 74273b:2|13
--operation mode is normal

B1_13_lut_out = BB1_q_a[22];
B1_13 = DFFEAS(B1_13_lut_out, 39, CLRN, , , , , , );


--B1_14 is 74273b:2|14
--operation mode is normal

B1_14_lut_out = BB1_q_a[21];
B1_14 = DFFEAS(B1_14_lut_out, 39, CLRN, , , , , , );


--B1_15 is 74273b:2|15
--operation mode is normal

B1_15_lut_out = BB1_q_a[20];
B1_15 = DFFEAS(B1_15_lut_out, 39, CLRN, , , , , , );


--B1_16 is 74273b:2|16
--operation mode is normal

B1_16_lut_out = BB1_q_a[19];
B1_16 = DFFEAS(B1_16_lut_out, 39, CLRN, , , , , , );


--B1_17 is 74273b:2|17
--operation mode is normal

B1_17_lut_out = BB1_q_a[18];
B1_17 = DFFEAS(B1_17_lut_out, 39, CLRN, , , , , , );


--B1_18 is 74273b:2|18
--operation mode is normal

B1_18_lut_out = BB1_q_a[17];
B1_18 = DFFEAS(B1_18_lut_out, 39, CLRN, , , , , , );


--B1_19 is 74273b:2|19
--operation mode is normal

B1_19_lut_out = BB1_q_a[16];
B1_19 = DFFEAS(B1_19_lut_out, 39, CLRN, , , , , , );


--B2_12 is 74273b:3|12
--operation mode is normal

B2_12_lut_out = BB1_q_a[15];
B2_12 = DFFEAS(B2_12_lut_out, 39, CLRN, , , , , , );


--B2_13 is 74273b:3|13
--operation mode is normal

B2_13_lut_out = BB1_q_a[14];
B2_13 = DFFEAS(B2_13_lut_out, 39, CLRN, , , , , , );


--B2_15 is 74273b:3|15
--operation mode is normal

B2_15_lut_out = BB1_q_a[12];
B2_15 = DFFEAS(B2_15_lut_out, 39, CLRN, , , , , , );


--B2_16 is 74273b:3|16
--operation mode is normal

B2_16_lut_out = BB1_q_a[11];
B2_16 = DFFEAS(B2_16_lut_out, 39, CLRN, , , , , , );


--B2_17 is 74273b:3|17
--operation mode is normal

B2_17_lut_out = BB1_q_a[10];
B2_17 = DFFEAS(B2_17_lut_out, 39, CLRN, , , , , , );


--B2_18 is 74273b:3|18
--operation mode is normal

B2_18_lut_out = BB1_q_a[9];
B2_18 = DFFEAS(B2_18_lut_out, 39, CLRN, , , , , , );


--B2_19 is 74273b:3|19
--operation mode is normal

B2_19_lut_out = BB1_q_a[8];
B2_19 = DFFEAS(B2_19_lut_out, 39, CLRN, , , , , , );


--B4_12 is 74273b:21|12
--operation mode is normal

B4_12_lut_out = BB1_q_a[7];
B4_12 = DFFEAS(B4_12_lut_out, 39, CLRN, , , , , , );


--B4_13 is 74273b:21|13
--operation mode is normal

B4_13_lut_out = BB1_q_a[6];
B4_13 = DFFEAS(B4_13_lut_out, 39, CLRN, , , , , , );


--B4_14 is 74273b:21|14
--operation mode is normal

B4_14_lut_out = BB1_q_a[5];
B4_14 = DFFEAS(B4_14_lut_out, 39, CLRN, , , , , , );


--B4_15 is 74273b:21|15
--operation mode is normal

B4_15_lut_out = BB1_q_a[4];
B4_15 = DFFEAS(B4_15_lut_out, 39, CLRN, , , , , , );


--B4_16 is 74273b:21|16
--operation mode is normal

B4_16_lut_out = BB1_q_a[3];
B4_16 = DFFEAS(B4_16_lut_out, 39, CLRN, , , , , , );


--B4_17 is 74273b:21|17
--operation mode is normal

B4_17_lut_out = BB1_q_a[2];
B4_17 = DFFEAS(B4_17_lut_out, 39, CLRN, , , , , , );


--B4_19 is 74273b:21|19
--operation mode is normal

B4_19_lut_out = BB1_q_a[0];
B4_19 = DFFEAS(B4_19_lut_out, 39, CLRN, , , , , , );


--BB1_q_a[23] is lpm_rom6:inst2|altsyncram:altsyncram_component|altsyncram_3mp:auto_generated|q_a[23]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 24
--Port A Input: Registered, Port A Output: Registered
BB1_q_a[23]_PORT_A_address = BUS(K1_9, K1_87, K1_99, K1_110, B3_15, B3_14, 24, 25);
BB1_q_a[23]_PORT_A_address_reg = DFFE(BB1_q_a[23]_PORT_A_address, BB1_q_a[23]_clock_0, , , );
BB1_q_a[23]_clock_0 = CLK;
BB1_q_a[23]_PORT_A_data_out = MEMORY(, , BB1_q_a[23]_PORT_A_address_reg, , , , , , BB1_q_a[23]_clock_0, , , , , );
BB1_q_a[23]_PORT_A_data_out_reg = DFFE(BB1_q_a[23]_PORT_A_data_out, BB1_q_a[23]_clock_0, , , );
BB1_q_a[23] = BB1_q_a[23]_PORT_A_data_out_reg[0];


--BB1_q_a[22] is lpm_rom6:inst2|altsyncram:altsyncram_component|altsyncram_3mp:auto_generated|q_a[22]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 24
--Port A Input: Registered, Port A Output: Registered
BB1_q_a[22]_PORT_A_address = BUS(K1_9, K1_87, K1_99, K1_110, B3_15, B3_14, 24, 25);
BB1_q_a[22]_PORT_A_address_reg = DFFE(BB1_q_a[22]_PORT_A_address, BB1_q_a[22]_clock_0, , , );
BB1_q_a[22]_clock_0 = CLK;
BB1_q_a[22]_PORT_A_data_out = MEMORY(, , BB1_q_a[22]_PORT_A_address_reg, , , , , , BB1_q_a[22]_clock_0, , , , , );
BB1_q_a[22]_PORT_A_data_out_reg = DFFE(BB1_q_a[22]_PORT_A_data_out, BB1_q_a[22]_clock_0, , , );
BB1_q_a[22] = BB1_q_a[22]_PORT_A_data_out_reg[0];


--BB1_q_a[21] is lpm_rom6:inst2|altsyncram:altsyncram_component|altsyncram_3mp:auto_generated|q_a[21]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 24
--Port A Input: Registered, Port A Output: Registered
BB1_q_a[21]_PORT_A_address = BUS(K1_9, K1_87, K1_99, K1_110, B3_15, B3_14, 24, 25);
BB1_q_a[21]_PORT_A_address_reg = DFFE(BB1_q_a[21]_PORT_A_address, BB1_q_a[21]_clock_0, , , );
BB1_q_a[21]_clock_0 = CLK;
BB1_q_a[21]_PORT_A_data_out = MEMORY(, , BB1_q_a[21]_PORT_A_address_reg, , , , , , BB1_q_a[21]_clock_0, , , , , );
BB1_q_a[21]_PORT_A_data_out_reg = DFFE(BB1_q_a[21]_PORT_A_data_out, BB1_q_a[21]_clock_0, , , );
BB1_q_a[21] = BB1_q_a[21]_PORT_A_data_out_reg[0];


--BB1_q_a[20] is lpm_rom6:inst2|altsyncram:altsyncram_component|altsyncram_3mp:auto_generated|q_a[20]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 24
--Port A Input: Registered, Port A Output: Registered
BB1_q_a[20]_PORT_A_address = BUS(K1_9, K1_87, K1_99, K1_110, B3_15, B3_14, 24, 25);
BB1_q_a[20]_PORT_A_address_reg = DFFE(BB1_q_a[20]_PORT_A_address, BB1_q_a[20]_clock_0, , , );
BB1_q_a[20]_clock_0 = CLK;
BB1_q_a[20]_PORT_A_data_out = MEMORY(, , BB1_q_a[20]_PORT_A_address_reg, , , , , , BB1_q_a[20]_clock_0, , , , , );
BB1_q_a[20]_PORT_A_data_out_reg = DFFE(BB1_q_a[20]_PORT_A_data_out, BB1_q_a[20]_clock_0, , , );
BB1_q_a[20] = BB1_q_a[20]_PORT_A_data_out_reg[0];


--BB1_q_a[19] is lpm_rom6:inst2|altsyncram:altsyncram_component|altsyncram_3mp:auto_generated|q_a[19]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 24
--Port A Input: Registered, Port A Output: Registered
BB1_q_a[19]_PORT_A_address = BUS(K1_9, K1_87, K1_99, K1_110, B3_15, B3_14, 24, 25);
BB1_q_a[19]_PORT_A_address_reg = DFFE(BB1_q_a[19]_PORT_A_address, BB1_q_a[19]_clock_0, , , );
BB1_q_a[19]_clock_0 = CLK;
BB1_q_a[19]_PORT_A_data_out = MEMORY(, , BB1_q_a[19]_PORT_A_address_reg, , , , , , BB1_q_a[19]_clock_0, , , , , );
BB1_q_a[19]_PORT_A_data_out_reg = DFFE(BB1_q_a[19]_PORT_A_data_out, BB1_q_a[19]_clock_0, , , );
BB1_q_a[19] = BB1_q_a[19]_PORT_A_data_out_reg[0];


--BB1_q_a[18] is lpm_rom6:inst2|altsyncram:altsyncram_component|altsyncram_3mp:auto_generated|q_a[18]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 24
--Port A Input: Registered, Port A Output: Registered
BB1_q_a[18]_PORT_A_address = BUS(K1_9, K1_87, K1_99, K1_110, B3_15, B3_14, 24, 25);
BB1_q_a[18]_PORT_A_address_reg = DFFE(BB1_q_a[18]_PORT_A_address, BB1_q_a[18]_clock_0, , , );
BB1_q_a[18]_clock_0 = CLK;
BB1_q_a[18]_PORT_A_data_out = MEMORY(, , BB1_q_a[18]_PORT_A_address_reg, , , , , , BB1_q_a[18]_clock_0, , , , , );
BB1_q_a[18]_PORT_A_data_out_reg = DFFE(BB1_q_a[18]_PORT_A_data_out, BB1_q_a[18]_clock_0, , , );
BB1_q_a[18] = BB1_q_a[18]_PORT_A_data_out_reg[0];


--BB1_q_a[17] is lpm_rom6:inst2|altsyncram:altsyncram_component|altsyncram_3mp:auto_generated|q_a[17]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 24
--Port A Input: Registered, Port A Output: Registered
BB1_q_a[17]_PORT_A_address = BUS(K1_9, K1_87, K1_99, K1_110, B3_15, B3_14, 24, 25);
BB1_q_a[17]_PORT_A_address_reg = DFFE(BB1_q_a[17]_PORT_A_address, BB1_q_a[17]_clock_0, , , );
BB1_q_a[17]_clock_0 = CLK;
BB1_q_a[17]_PORT_A_data_out = MEMORY(, , BB1_q_a[17]_PORT_A_address_reg, , , , , , BB1_q_a[17]_clock_0, , , , , );
BB1_q_a[17]_PORT_A_data_out_reg = DFFE(BB1_q_a[17]_PORT_A_data_out, BB1_q_a[17]_clock_0, , , );
BB1_q_a[17] = BB1_q_a[17]_PORT_A_data_out_reg[0];


--BB1_q_a[16] is lpm_rom6:inst2|altsyncram:altsyncram_component|altsyncram_3mp:auto_generated|q_a[16]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 24
--Port A Input: Registered, Port A Output: Registered
BB1_q_a[16]_PORT_A_address = BUS(K1_9, K1_87, K1_99, K1_110, B3_15, B3_14, 24, 25);
BB1_q_a[16]_PORT_A_address_reg = DFFE(BB1_q_a[16]_PORT_A_address, BB1_q_a[16]_clock_0, , , );
BB1_q_a[16]_clock_0 = CLK;
BB1_q_a[16]_PORT_A_data_out = MEMORY(, , BB1_q_a[16]_PORT_A_address_reg, , , , , , BB1_q_a[16]_clock_0, , , , , );
BB1_q_a[16]_PORT_A_data_out_reg = DFFE(BB1_q_a[16]_PORT_A_data_out, BB1_q_a[16]_clock_0, , , );
BB1_q_a[16] = BB1_q_a[16]_PORT_A_data_out_reg[0];


--W3L2 is 8cpu:92|alu:62|lpm_add_sub:1|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~156
--operation mode is arithmetic

W3L2_carry_eqn = W3L5;
W3L2 = B8_12 $ B7_12 $ W3L2_carry_eqn;

--W3L3 is 8cpu:92|alu:62|lpm_add_sub:1|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~158
--operation mode is arithmetic

W3L3 = CARRY(B8_12 & !B7_12 & !W3L5 # !B8_12 & (!W3L5 # !B7_12));


--F1_11 is dcf:84|11
--operation mode is normal

F1_11_lut_out = VCC;
F1_11 = DFFEAS(F1_11_lut_out, START, !A1L31, , , , , , );


--AB1_11 is sequence:103|74393b:25|11
--operation mode is normal

AB1_11 = AB1_1 & AB1_3 & AB1_5;


--AB1L4 is sequence:103|74393b:25|8~8
--operation mode is normal

AB1L4 = AB1_1 & AB1_3;


--BB1_q_a[13] is lpm_rom6:inst2|altsyncram:altsyncram_component|altsyncram_3mp:auto_generated|q_a[13]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 24