mycpu.hif

Quartus II 5.0下写的一个单总线架构的CPU设计

8cpu:92|alu:62|lpm_add_sub:1|altshift:carry_ext_latency_ffs
8cpu:92|alu:62|lpm_add_sub:1|altshift:oflow_ext_latency_ffs
}
# end
# entity
74273b
# case_insensitive
# source_file
d:|quartus50|libraries|others|maxplus2|74273b.bdf
1107572830
23
# storage
db|mycpu.(9).cnf
db|mycpu.(9).cnf
# hierarchies {
8cpu:92|alu:62|74273b:4
8cpu:92|alu:62|74273b:5
8cpu:92|alu:62|74273b:11
8cpu:92|74273b:3
8cpu:92|74273b:7
74273b:21
74273b:3
74273b:10
74273b:2
}
# end
# entity
busmux
# case_insensitive
# source_file
d:|quartus50|libraries|megafunctions|BUSMUX.tdf
1114012436
6
# storage
db|mycpu.(10).cnf
db|mycpu.(10).cnf
# user_parameter {
WIDTH
8
PARAMETER_UNKNOWN
USR
}
# used_port {
dataa0
dataa1
dataa2
dataa3
dataa4
dataa5
dataa6
dataa7
datab0
datab1
datab2
datab3
datab4
datab5
datab6
datab7
result0
result1
result2
result3
result4
result5
result6
result7
sel
}
# include_file {
d:|quartus50|libraries|megafunctions|lpm_mux.inc
1107574776
}
# hierarchies {
8cpu:92|busmux:49
8cpu:92|busmux:33
8cpu:92|busmux:31
8cpu:92|busmux:48
}
# end
# entity
lpm_mux
# case_insensitive
# source_file
d:|quartus50|libraries|megafunctions|lpm_mux.tdf
1114012454
6
# storage
db|mycpu.(11).cnf
db|mycpu.(11).cnf
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
8
PARAMETER_UNKNOWN
USR
LPM_SIZE
2
PARAMETER_UNKNOWN
USR
LPM_WIDTHS
1
PARAMETER_UNKNOWN
USR
LPM_PIPELINE
0
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
mux_afc
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
}
# used_port {
data0_0
data0_1
data0_2
data0_3
data0_4
data0_5
data0_6
data0_7
data1_0
data1_1
data1_2
data1_3
data1_4
data1_5
data1_6
data1_7
sel0
result0
result1
result2
result3
result4
result5
result6
result7
}
# include_file {
d:|quartus50|libraries|megafunctions|bypassff.inc
1107573920
d:|quartus50|libraries|megafunctions|altshift.inc
1107573438
d:|quartus50|libraries|megafunctions|aglobal50.inc
1114012420
d:|quartus50|libraries|megafunctions|muxlut.inc
1107575250
}
# hierarchies {
8cpu:92|busmux:49|lpm_mux:$00000
8cpu:92|busmux:33|lpm_mux:$00000
8cpu:92|busmux:31|lpm_mux:$00000
8cpu:92|busmux:48|lpm_mux:$00000
}
# end
# entity
altsyncram
# case_insensitive
# source_file
d:|quartus50|libraries|megafunctions|altsyncram.tdf
1114012438
6
# storage
db|mycpu.(14).cnf
db|mycpu.(14).cnf
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
SINGLE_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
8
PARAMETER_DEC
USR
WIDTHAD_A
8
PARAMETER_DEC
USR
NUMWORDS_A
256
PARAMETER_DEC
USR
OUTDATA_REG_A
CLOCK0
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
INIT_FILE
ram2.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_rs21
PARAMETER_UNKNOWN
USR
}
# used_port {
address_a
address_a
address_a
address_a
address_a
address_a
address_a
address_a
clock0
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
wren_a
}
# include_file {
d:|quartus50|libraries|megafunctions|aglobal50.inc
1114012420
d:|quartus50|libraries|megafunctions|lpm_mux.inc
1107574776
d:|quartus50|libraries|megafunctions|stratix_ram_block.inc
1107575592
d:|quartus50|libraries|megafunctions|lpm_decode.inc
1107574570
d:|quartus50|libraries|megafunctions|altsyncram.inc
1107573506
d:|quartus50|libraries|megafunctions|altrom.inc
1107573422
d:|quartus50|libraries|megafunctions|a_rdenreg.inc
1107572148
d:|quartus50|libraries|megafunctions|altram.inc
1107573384
d:|quartus50|libraries|megafunctions|altdpram.inc
1107573082
d:|quartus50|libraries|megafunctions|altqpram.inc
1107573362
}
# hierarchies {
8cpu:92|lpm_ram_dq0:inst|altsyncram:altsyncram_component
}
# end
# entity
74161
# case_insensitive
# source_file
d:|quartus50|libraries|others|maxplus2|74161.tdf
1107570978
6
# storage
db|mycpu.(19).cnf
db|mycpu.(19).cnf
# user_parameter {
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
A
B
C
CLK
CLRN
D
ENP
ENT
LDN
QA
QB
QC
QD
RCO
}
# include_file {
d:|quartus50|libraries|megafunctions|aglobal.inc
1114012420
}
# hierarchies {
8cpu:92|pc:65|74161:8
}
# end
# entity
f74161
# case_insensitive
# source_file
d:|quartus50|libraries|others|maxplus2|f74161.bdf
1107578552
23
# storage
db|mycpu.(20).cnf
db|mycpu.(20).cnf
# hierarchies {
8cpu:92|pc:65|74161:8|f74161:sub
8cpu:92|pc:65|74161:9|f74161:sub
74161:12|f74161:sub
}
# end
# entity
74161
# case_insensitive
# source_file
d:|quartus50|libraries|others|maxplus2|74161.tdf
1107570978
6
# storage
db|mycpu.(21).cnf
db|mycpu.(21).cnf
# user_parameter {
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
A
B
C
CLK
CLRN
D
ENP
ENT
LDN
QA
QB
QC
QD
}
# include_file {
d:|quartus50|libraries|megafunctions|aglobal.inc
1114012420
}
# hierarchies {
8cpu:92|pc:65|74161:9
}
# end
# entity
altsyncram
# case_insensitive
# source_file
d:|quartus50|libraries|megafunctions|altsyncram.tdf
1114012438
6
# storage
db|mycpu.(27).cnf
db|mycpu.(27).cnf
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
ROM
PARAMETER_UNKNOWN
USR
WIDTH_A
24
PARAMETER_DEC
USR
WIDTHAD_A
8
PARAMETER_DEC
USR
NUMWORDS_A
256
PARAMETER_DEC
USR
OUTDATA_REG_A
CLOCK0
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
INIT_FILE
rom.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_3mp
PARAMETER_UNKNOWN
USR
}
# used_port {
address_a
address_a
address_a
address_a
address_a
address_a
address_a
address_a
clock0
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
}
# include_file {
d:|quartus50|libraries|megafunctions|aglobal50.inc
1114012420
d:|quartus50|libraries|megafunctions|lpm_mux.inc
1107574776
d:|quartus50|libraries|megafunctions|stratix_ram_block.inc
1107575592
d:|quartus50|libraries|megafunctions|lpm_decode.inc
1107574570
d:|quartus50|libraries|megafunctions|altsyncram.inc
1107573506
d:|quartus50|libraries|megafunctions|altrom.inc
1107573422
d:|quartus50|libraries|megafunctions|a_rdenreg.inc
1107572148
d:|quartus50|libraries|megafunctions|altram.inc
1107573384
d:|quartus50|libraries|megafunctions|altdpram.inc
1107573082
d:|quartus50|libraries|megafunctions|altqpram.inc
1107573362
}
# hierarchies {
lpm_rom6:inst2|altsyncram:altsyncram_component
}
# end
# entity
74161
# case_insensitive
# source_file
d:|quartus50|libraries|others|maxplus2|74161.tdf
1107570978
6
# storage
db|mycpu.(30).cnf
db|mycpu.(30).cnf
# user_parameter {
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
CLK
CLRN
ENP
ENT
LDN
QA
QB
QC
QD
}
# include_file {
d:|quartus50|libraries|megafunctions|aglobal.inc
1114012420
}
# hierarchies {
74161:12
}
# end
# entity
cpu001
# case_insensitive
# source_file
cpu001.bdf
1197381104
23
# storage
db|mycpu.(0).cnf
db|mycpu.(0).cnf
# hierarchies {
|
}
# end
# complete