mycpu.hif

Quartus II 5.0下写的一个单总线架构的CPU设计

Version 5.0 Build 148 04/26/2005 SJ Full Version
32
1614
OFF
OFF
OFF
OFF
OFF
FV_OFF
VRSM_ON
VHSM_ON
0
# entity
alu
# case_insensitive
# source_file
alu.bdf
978061792
23
# storage
db|mycpu.(2).cnf
db|mycpu.(2).cnf
# hierarchies {
8cpu:92|alu:62
}
# end
# entity
mux_afc
# case_insensitive
# source_file
db|mux_afc.tdf
1194942912
6
# storage
db|mycpu.(12).cnf
db|mycpu.(12).cnf
# used_port {
data0
data1
data2
data3
data4
data5
data6
data7
data8
data9
data10
data11
data12
data13
data14
data15
sel0
result0
result1
result2
result3
result4
result5
result6
result7
}
# hierarchies {
8cpu:92|busmux:49|lpm_mux:$00000|mux_afc:auto_generated
8cpu:92|busmux:33|lpm_mux:$00000|mux_afc:auto_generated
8cpu:92|busmux:31|lpm_mux:$00000|mux_afc:auto_generated
8cpu:92|busmux:48|lpm_mux:$00000|mux_afc:auto_generated
}
# end
# entity
bi74670
# case_insensitive
# source_file
bi74670.bdf
982031518
23
# storage
db|mycpu.(16).cnf
db|mycpu.(16).cnf
# hierarchies {
8cpu:92|bi74670:67
}
# end
# entity
74670c
# case_insensitive
# source_file
74670c.bdf
977902370
23
# storage
db|mycpu.(17).cnf
db|mycpu.(17).cnf
# hierarchies {
8cpu:92|bi74670:67|74670c:34
8cpu:92|bi74670:67|74670c:32
}
# end
# entity
pc
# case_insensitive
# source_file
pc.bdf
982031104
23
# storage
db|mycpu.(18).cnf
db|mycpu.(18).cnf
# hierarchies {
8cpu:92|pc:65
}
# end
# entity
sequence
# case_insensitive
# source_file
sequence.bdf
1048736690
23
# storage
db|mycpu.(22).cnf
db|mycpu.(22).cnf
# hierarchies {
sequence:103
}
# end
# entity
74393b
# case_insensitive
# source_file
74393b.bdf
978492424
23
# storage
db|mycpu.(23).cnf
db|mycpu.(23).cnf
# hierarchies {
sequence:103|74393b:25
}
# end
# entity
dcf
# case_insensitive
# source_file
dcf.bdf
979185130
23
# storage
db|mycpu.(24).cnf
db|mycpu.(24).cnf
# hierarchies {
dcf:84
}
# end
# entity
1to8
# case_insensitive
# source_file
1to8.bdf
977104738
23
# storage
db|mycpu.(25).cnf
db|mycpu.(25).cnf
# hierarchies {
1to8:43
1to8:42
1to8:32
1to8:41
}
# end
# entity
altsyncram_3mp
# case_insensitive
# source_file
db|altsyncram_3mp.tdf
1195561678
6
# storage
db|mycpu.(28).cnf
db|mycpu.(28).cnf
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_a7
clock0
q_a0
q_a1
q_a2
q_a3
q_a4
q_a5
q_a6
q_a7
q_a8
q_a9
q_a10
q_a11
q_a12
q_a13
q_a14
q_a15
q_a16
q_a17
q_a18
q_a19
q_a20
q_a21
q_a22
q_a23
}
# memory_file {
rom.mif
1195566714
}
# hierarchies {
lpm_rom6:inst2|altsyncram:altsyncram_component|altsyncram_3mp:auto_generated
}
# end
# entity
8to1
# case_insensitive
# source_file
8to1.bdf
977450846
23
# storage
db|mycpu.(29).cnf
db|mycpu.(29).cnf
# hierarchies {
8to1:22
}
# end
# entity
lpm_rom6
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
lpm_rom6.v
1132549570
7
# storage
db|mycpu.(26).cnf
db|mycpu.(26).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
lpm_rom6:inst2
}
# end
# entity
altsyncram_9r21
# case_insensitive
# source_file
db|altsyncram_9r21.tdf
1195553458
6
# storage
db|mycpu.(15).cnf
db|mycpu.(15).cnf
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_a
data_a0
data_a1
data_a2
data_a3
data_a4
data_a5
data_a6
data_a7
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_a7
clock0
q_a0
q_a1
q_a2
q_a3
q_a4
q_a5
q_a6
q_a7
}
# memory_file {
ram.mif
1132551834
}
# end
# entity
8cpu
# case_insensitive
# source_file
8cpu.bdf
1132553748
23
# storage
db|mycpu.(1).cnf
db|mycpu.(1).cnf
# hierarchies {
8cpu:92
}
# end
# entity
lpm_ram_dq0
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
lpm_ram_dq0.v
1132553736
7
# storage
db|mycpu.(13).cnf
db|mycpu.(13).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
8cpu:92|lpm_ram_dq0:inst
}
# end
# entity
altsyncram_rs21
# case_insensitive
# source_file
db|altsyncram_rs21.tdf
1132553752
6
# storage
db|mycpu.(32).cnf
db|mycpu.(32).cnf
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_a
data_a0
data_a1
data_a2
data_a3
data_a4
data_a5
data_a6
data_a7
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_a7
clock0
q_a0
q_a1
q_a2
q_a3
q_a4
q_a5
q_a6
q_a7
}
# memory_file {
ram2.mif
1132556190
}
# hierarchies {
8cpu:92|lpm_ram_dq0:inst|altsyncram:altsyncram_component|altsyncram_rs21:auto_generated
}
# end
# entity
lpm_add_sub
# case_insensitive
# source_file
d:|quartus50|libraries|megafunctions|LPM_ADD_SUB.tdf
1114012446
6
# storage
db|mycpu.(3).cnf
db|mycpu.(3).cnf
# user_parameter {
LPM_WIDTH
8
PARAMETER_UNKNOWN
USR
LPM_REPRESENTATION
SIGNED
PARAMETER_UNKNOWN
USR
LPM_DIRECTION
ADD
PARAMETER_UNKNOWN
USR
ONE_INPUT_IS_CONSTANT
NO
PARAMETER_UNKNOWN
DEF
LPM_PIPELINE
0
PARAMETER_UNKNOWN
USR
MAXIMIZE_SPEED
5
PARAMETER_UNKNOWN
DEF
REGISTERED_AT_END
0
PARAMETER_UNKNOWN
DEF
OPTIMIZE_FOR_SPEED
5
PARAMETER_UNKNOWN
USR
USE_CS_BUFFERS
1
PARAMETER_UNKNOWN
DEF
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
USE_WYS
OFF
PARAMETER_UNKNOWN
DEF
STYLE
FAST
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
add_sub_4pg
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
cin
cout
dataa0
dataa1
dataa2
dataa3
dataa4
dataa5
dataa6
dataa7
datab0
datab1
datab2
datab3
datab4
datab5
datab6
datab7
result0
result1
result2
result3
result4
result5
result6
result7
}
# include_file {
d:|quartus50|libraries|megafunctions|addcore.inc
1107572218
d:|quartus50|libraries|megafunctions|look_add.inc
1107574364
d:|quartus50|libraries|megafunctions|bypassff.inc
1107573920
d:|quartus50|libraries|megafunctions|altshift.inc
1107573438
d:|quartus50|libraries|megafunctions|alt_stratix_add_sub.inc
1107572606
d:|quartus50|libraries|megafunctions|alt_mercury_add_sub.inc
1107572592
d:|quartus50|libraries|megafunctions|aglobal50.inc
1114012420
}
# hierarchies {
8cpu:92|alu:62|lpm_add_sub:1
}
# end
# entity
addcore
# case_insensitive
# source_file
d:|quartus50|libraries|megafunctions|addcore.tdf
1114012446
6
# storage
db|mycpu.(4).cnf
db|mycpu.(4).cnf
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
width
8
PARAMETER_UNKNOWN
USR
REPRESENTATION
SIGNED
PARAMETER_UNKNOWN
USR
DIRECTION
ADD
PARAMETER_UNKNOWN
USR
USE_CS_BUFFERS
1
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
}
# used_port {
dataa0
dataa1
dataa2
dataa3
dataa4
dataa5
dataa6
dataa7
datab0
datab1
datab2
datab3
datab4
datab5
datab6
datab7
cin
result0
result1
result2
result3
result4
result5
result6
result7
cout
}
# include_file {
d:|quartus50|libraries|megafunctions|addcore.inc
1107572218
d:|quartus50|libraries|megafunctions|aglobal50.inc
1114012420
d:|quartus50|libraries|megafunctions|a_csnbuffer.inc
1107571892
}
# hierarchies {
8cpu:92|alu:62|lpm_add_sub:1|addcore:adder
}
# end
# entity
a_csnbuffer
# case_insensitive
# source_file
d:|quartus50|libraries|megafunctions|a_csnbuffer.tdf
1114012448
6
# storage
db|mycpu.(5).cnf
db|mycpu.(5).cnf
# user_parameter {
WIDTH
8
PARAMETER_UNKNOWN
USR
NEED_CARRY
0
PARAMETER_UNKNOWN
DEF
USE_CS_BUFFERS
1
PARAMETER_UNKNOWN
USR
}
# used_port {
sin0
sout0
}
# hierarchies {
8cpu:92|alu:62|lpm_add_sub:1|addcore:adder|a_csnbuffer:oflow_node
8cpu:92|alu:62|lpm_add_sub:1|addcore:adder|a_csnbuffer:cout_node
}
# end
# entity
a_csnbuffer
# case_insensitive
# source_file
d:|quartus50|libraries|megafunctions|a_csnbuffer.tdf
1114012448
6
# storage
db|mycpu.(6).cnf
db|mycpu.(6).cnf
# user_parameter {
WIDTH
8
PARAMETER_UNKNOWN
USR
NEED_CARRY
1
PARAMETER_UNKNOWN
USR
USE_CS_BUFFERS
1
PARAMETER_UNKNOWN
USR
}
# used_port {
sin0
sin1
sin2
sin3
sin4
sin5
sin6
sin7
cin0
cin1
cin2
cin3
cin4
cin5
cin6
cin7
sout0
sout1
sout2
sout3
sout4
sout5
sout6
sout7
cout0
cout1
cout2
cout3
cout4
cout5
cout6
cout7
}
# hierarchies {
8cpu:92|alu:62|lpm_add_sub:1|addcore:adder|a_csnbuffer:result_node
}
# end
# entity
altshift
# case_insensitive
# source_file
d:|quartus50|libraries|megafunctions|altshift.tdf
1114012454
6
# storage
db|mycpu.(7).cnf
db|mycpu.(7).cnf
# user_parameter {
WIDTH
8
PARAMETER_UNKNOWN
USR
DEPTH
0
PARAMETER_UNKNOWN
USR
}
# used_port {
data0
data1
data2
data3
data4
data5
data6
data7
result0
result1
result2
result3
result4
result5
result6
result7
}
# hierarchies {
8cpu:92|alu:62|lpm_add_sub:1|altshift:result_ext_latency_ffs
}
# end
# entity
altshift
# case_insensitive
# source_file
d:|quartus50|libraries|megafunctions|altshift.tdf
1114012454
6
# storage
db|mycpu.(8).cnf
db|mycpu.(8).cnf
# user_parameter {
WIDTH
1
PARAMETER_UNKNOWN
USR
DEPTH
0
PARAMETER_UNKNOWN
USR
}
# used_port {
data0
result0
}
# hierarchies {