f_div.vhd

Quartus II 5.0下写的一个单总线架构的CPU设计

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic       
-- functions, and any output files any of the foregoing           
-- (including device programming or simulation files), and any    
-- associated documentation or information are expressly subject  
-- to the terms and conditions of the Altera Program License      
-- Subscription Agreement, Altera MegaCore Function License       
-- Agreement, or other applicable license agreement, including,   
-- without limitation, that your use is for the sole purpose of   
-- programming logic devices manufactured by Altera and sold by   
-- Altera or its authorized distributors.  Please refer to the    
-- applicable agreement for further details.

-- PROGRAM "Quartus II"
-- VERSION "Version 5.0 Build 148 04/26/2005 SJ Full Version"

LIBRARY ieee;
USE ieee.std_logic_1164.all; 

LIBRARY work;

ENTITY F_Div IS 
	port
	(
		inClk :  IN  STD_LOGIC;
		outCLK :  OUT  STD_LOGIC
	);
END F_Div;

ARCHITECTURE bdf_type OF F_Div IS 

signal	SYNTHESIZED_WIRE_35 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_2 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_4 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_6 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_8 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_10 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_12 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_14 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_36 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_16 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_18 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_20 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_22 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_24 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_26 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_28 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_30 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_32 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_34 :  STD_LOGIC;


BEGIN 
SYNTHESIZED_WIRE_35 <= '1';
SYNTHESIZED_WIRE_36 <= '1';



process(inClk)
variable SYNTHESIZED_WIRE_2_synthesized_var : STD_LOGIC;
begin
if (rising_edge(inClk)) then
	SYNTHESIZED_WIRE_2_synthesized_var := SYNTHESIZED_WIRE_2_synthesized_var XOR SYNTHESIZED_WIRE_35;
end if;
	SYNTHESIZED_WIRE_2 <= SYNTHESIZED_WIRE_2_synthesized_var;
end process;

process(SYNTHESIZED_WIRE_2)
variable SYNTHESIZED_WIRE_4_synthesized_var : STD_LOGIC;
begin
if (rising_edge(SYNTHESIZED_WIRE_2)) then
	SYNTHESIZED_WIRE_4_synthesized_var := SYNTHESIZED_WIRE_4_synthesized_var XOR SYNTHESIZED_WIRE_35;
end if;
	SYNTHESIZED_WIRE_4 <= SYNTHESIZED_WIRE_4_synthesized_var;
end process;

process(SYNTHESIZED_WIRE_4)
variable SYNTHESIZED_WIRE_6_synthesized_var : STD_LOGIC;
begin
if (rising_edge(SYNTHESIZED_WIRE_4)) then
	SYNTHESIZED_WIRE_6_synthesized_var := SYNTHESIZED_WIRE_6_synthesized_var XOR SYNTHESIZED_WIRE_35;
end if;
	SYNTHESIZED_WIRE_6 <= SYNTHESIZED_WIRE_6_synthesized_var;
end process;

process(SYNTHESIZED_WIRE_6)
variable SYNTHESIZED_WIRE_8_synthesized_var : STD_LOGIC;
begin
if (rising_edge(SYNTHESIZED_WIRE_6)) then
	SYNTHESIZED_WIRE_8_synthesized_var := SYNTHESIZED_WIRE_8_synthesized_var XOR SYNTHESIZED_WIRE_35;
end if;
	SYNTHESIZED_WIRE_8 <= SYNTHESIZED_WIRE_8_synthesized_var;
end process;

process(SYNTHESIZED_WIRE_8)
variable SYNTHESIZED_WIRE_10_synthesized_var : STD_LOGIC;
begin
if (rising_edge(SYNTHESIZED_WIRE_8)) then
	SYNTHESIZED_WIRE_10_synthesized_var := SYNTHESIZED_WIRE_10_synthesized_var XOR SYNTHESIZED_WIRE_35;
end if;
	SYNTHESIZED_WIRE_10 <= SYNTHESIZED_WIRE_10_synthesized_var;
end process;

process(SYNTHESIZED_WIRE_10)
variable SYNTHESIZED_WIRE_12_synthesized_var : STD_LOGIC;
begin
if (rising_edge(SYNTHESIZED_WIRE_10)) then
	SYNTHESIZED_WIRE_12_synthesized_var := SYNTHESIZED_WIRE_12_synthesized_var XOR SYNTHESIZED_WIRE_35;
end if;
	SYNTHESIZED_WIRE_12 <= SYNTHESIZED_WIRE_12_synthesized_var;
end process;

process(SYNTHESIZED_WIRE_12)
variable SYNTHESIZED_WIRE_14_synthesized_var : STD_LOGIC;
begin
if (rising_edge(SYNTHESIZED_WIRE_12)) then
	SYNTHESIZED_WIRE_14_synthesized_var := SYNTHESIZED_WIRE_14_synthesized_var XOR SYNTHESIZED_WIRE_35;
end if;
	SYNTHESIZED_WIRE_14 <= SYNTHESIZED_WIRE_14_synthesized_var;
end process;

process(SYNTHESIZED_WIRE_14)
variable SYNTHESIZED_WIRE_16_synthesized_var : STD_LOGIC;
begin
if (rising_edge(SYNTHESIZED_WIRE_14)) then
	SYNTHESIZED_WIRE_16_synthesized_var := SYNTHESIZED_WIRE_16_synthesized_var XOR SYNTHESIZED_WIRE_35;
end if;
	SYNTHESIZED_WIRE_16 <= SYNTHESIZED_WIRE_16_synthesized_var;
end process;

process(SYNTHESIZED_WIRE_16)
variable SYNTHESIZED_WIRE_18_synthesized_var : STD_LOGIC;
begin
if (rising_edge(SYNTHESIZED_WIRE_16)) then
	SYNTHESIZED_WIRE_18_synthesized_var := SYNTHESIZED_WIRE_18_synthesized_var XOR SYNTHESIZED_WIRE_36;
end if;
	SYNTHESIZED_WIRE_18 <= SYNTHESIZED_WIRE_18_synthesized_var;
end process;

process(SYNTHESIZED_WIRE_18)
variable SYNTHESIZED_WIRE_20_synthesized_var : STD_LOGIC;
begin
if (rising_edge(SYNTHESIZED_WIRE_18)) then
	SYNTHESIZED_WIRE_20_synthesized_var := SYNTHESIZED_WIRE_20_synthesized_var XOR SYNTHESIZED_WIRE_36;
end if;
	SYNTHESIZED_WIRE_20 <= SYNTHESIZED_WIRE_20_synthesized_var;
end process;

process(SYNTHESIZED_WIRE_20)
variable SYNTHESIZED_WIRE_22_synthesized_var : STD_LOGIC;
begin
if (rising_edge(SYNTHESIZED_WIRE_20)) then
	SYNTHESIZED_WIRE_22_synthesized_var := SYNTHESIZED_WIRE_22_synthesized_var XOR SYNTHESIZED_WIRE_36;
end if;
	SYNTHESIZED_WIRE_22 <= SYNTHESIZED_WIRE_22_synthesized_var;
end process;

process(SYNTHESIZED_WIRE_22)
variable SYNTHESIZED_WIRE_24_synthesized_var : STD_LOGIC;
begin
if (rising_edge(SYNTHESIZED_WIRE_22)) then
	SYNTHESIZED_WIRE_24_synthesized_var := SYNTHESIZED_WIRE_24_synthesized_var XOR SYNTHESIZED_WIRE_36;
end if;
	SYNTHESIZED_WIRE_24 <= SYNTHESIZED_WIRE_24_synthesized_var;
end process;

process(SYNTHESIZED_WIRE_24)
variable SYNTHESIZED_WIRE_26_synthesized_var : STD_LOGIC;
begin
if (rising_edge(SYNTHESIZED_WIRE_24)) then
	SYNTHESIZED_WIRE_26_synthesized_var := SYNTHESIZED_WIRE_26_synthesized_var XOR SYNTHESIZED_WIRE_36;
end if;
	SYNTHESIZED_WIRE_26 <= SYNTHESIZED_WIRE_26_synthesized_var;
end process;

process(SYNTHESIZED_WIRE_26)
variable SYNTHESIZED_WIRE_28_synthesized_var : STD_LOGIC;
begin
if (rising_edge(SYNTHESIZED_WIRE_26)) then
	SYNTHESIZED_WIRE_28_synthesized_var := SYNTHESIZED_WIRE_28_synthesized_var XOR SYNTHESIZED_WIRE_36;
end if;
	SYNTHESIZED_WIRE_28 <= SYNTHESIZED_WIRE_28_synthesized_var;
end process;

process(SYNTHESIZED_WIRE_28)
variable SYNTHESIZED_WIRE_30_synthesized_var : STD_LOGIC;
begin
if (rising_edge(SYNTHESIZED_WIRE_28)) then
	SYNTHESIZED_WIRE_30_synthesized_var := SYNTHESIZED_WIRE_30_synthesized_var XOR SYNTHESIZED_WIRE_36;
end if;
	SYNTHESIZED_WIRE_30 <= SYNTHESIZED_WIRE_30_synthesized_var;
end process;

process(SYNTHESIZED_WIRE_30)
variable SYNTHESIZED_WIRE_32_synthesized_var : STD_LOGIC;
begin
if (rising_edge(SYNTHESIZED_WIRE_30)) then
	SYNTHESIZED_WIRE_32_synthesized_var := SYNTHESIZED_WIRE_32_synthesized_var XOR SYNTHESIZED_WIRE_36;
end if;
	SYNTHESIZED_WIRE_32 <= SYNTHESIZED_WIRE_32_synthesized_var;
end process;

process(SYNTHESIZED_WIRE_32)
variable SYNTHESIZED_WIRE_34_synthesized_var : STD_LOGIC;
begin
if (rising_edge(SYNTHESIZED_WIRE_32)) then
	SYNTHESIZED_WIRE_34_synthesized_var := SYNTHESIZED_WIRE_34_synthesized_var XOR SYNTHESIZED_WIRE_36;
end if;
	SYNTHESIZED_WIRE_34 <= SYNTHESIZED_WIRE_34_synthesized_var;
end process;

process(SYNTHESIZED_WIRE_34)
variable outCLK_synthesized_var : STD_LOGIC;
begin
if (rising_edge(SYNTHESIZED_WIRE_34)) then
	outCLK_synthesized_var := outCLK_synthesized_var XOR SYNTHESIZED_WIRE_36;
end if;
	outCLK <= outCLK_synthesized_var;
end process;

END;