mycpu.fit.eqn

Quartus II 5.0下写的一个单总线架构的CPU设计

--S4L61 is 8cpu:92|busmux:49|lpm_mux:$00000|mux_afc:auto_generated|w_result97w~87 at LC_X24_Y6_N2
--operation mode is normal

B1_13_qfbk = B1_13;
S4L61 = H1_33 & (B1_13_qfbk & !B1_15);

--B1_13 is 74273b:2|13 at LC_X24_Y6_N2
--operation mode is normal

B1_13 = DFFEAS(S4L61, GLOBAL(39), CLRN, , , BB1_q_a[22], , , VCC);


--Z1_q_a[7] is 8cpu:92|lpm_ram_dq0:inst|altsyncram:altsyncram_component|altsyncram_rs21:auto_generated|q_a[7] at M4K_X17_Y7
--RAM Block Operation Mode: Single Port
--Port A Depth: 256, Port A Width: 8
--Port A Logical Depth: 256, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
Z1_q_a[7]_PORT_A_data_in = BUS(K3L22, K3L91, K3L41, K3L2, K2L12, K2L61, K2L11, K2L2);
Z1_q_a[7]_PORT_A_data_in_reg = DFFE(Z1_q_a[7]_PORT_A_data_in, Z1_q_a[7]_clock_0, , , );
Z1_q_a[7]_PORT_A_address = BUS(B5_19, B5_18, B5_17, B5_16, B5_15, B5_14, B5_13, B5_12);
Z1_q_a[7]_PORT_A_address_reg = DFFE(Z1_q_a[7]_PORT_A_address, Z1_q_a[7]_clock_0, , , );
Z1_q_a[7]_PORT_A_write_enable = 70;
Z1_q_a[7]_PORT_A_write_enable_reg = DFFE(Z1_q_a[7]_PORT_A_write_enable, Z1_q_a[7]_clock_0, , , );
Z1_q_a[7]_clock_0 = GLOBAL(CLK);
Z1_q_a[7]_PORT_A_data_out = MEMORY(Z1_q_a[7]_PORT_A_data_in_reg, , Z1_q_a[7]_PORT_A_address_reg, , Z1_q_a[7]_PORT_A_write_enable_reg, , , , Z1_q_a[7]_clock_0, , , , , );
Z1_q_a[7]_PORT_A_data_out_reg = DFFE(Z1_q_a[7]_PORT_A_data_out, Z1_q_a[7]_clock_0, , , );
Z1_q_a[7] = Z1_q_a[7]_PORT_A_data_out_reg[0];

--Z1_q_a[0] is 8cpu:92|lpm_ram_dq0:inst|altsyncram:altsyncram_component|altsyncram_rs21:auto_generated|q_a[0] at M4K_X17_Y7
Z1_q_a[7]_PORT_A_data_in = BUS(K3L22, K3L91, K3L41, K3L2, K2L12, K2L61, K2L11, K2L2);
Z1_q_a[7]_PORT_A_data_in_reg = DFFE(Z1_q_a[7]_PORT_A_data_in, Z1_q_a[7]_clock_0, , , );
Z1_q_a[7]_PORT_A_address = BUS(B5_19, B5_18, B5_17, B5_16, B5_15, B5_14, B5_13, B5_12);
Z1_q_a[7]_PORT_A_address_reg = DFFE(Z1_q_a[7]_PORT_A_address, Z1_q_a[7]_clock_0, , , );
Z1_q_a[7]_PORT_A_write_enable = 70;
Z1_q_a[7]_PORT_A_write_enable_reg = DFFE(Z1_q_a[7]_PORT_A_write_enable, Z1_q_a[7]_clock_0, , , );
Z1_q_a[7]_clock_0 = GLOBAL(CLK);
Z1_q_a[7]_PORT_A_data_out = MEMORY(Z1_q_a[7]_PORT_A_data_in_reg, , Z1_q_a[7]_PORT_A_address_reg, , Z1_q_a[7]_PORT_A_write_enable_reg, , , , Z1_q_a[7]_clock_0, , , , , );
Z1_q_a[7]_PORT_A_data_out_reg = DFFE(Z1_q_a[7]_PORT_A_data_out, Z1_q_a[7]_clock_0, , , );
Z1_q_a[0] = Z1_q_a[7]_PORT_A_data_out_reg[7];

--Z1_q_a[1] is 8cpu:92|lpm_ram_dq0:inst|altsyncram:altsyncram_component|altsyncram_rs21:auto_generated|q_a[1] at M4K_X17_Y7
Z1_q_a[7]_PORT_A_data_in = BUS(K3L22, K3L91, K3L41, K3L2, K2L12, K2L61, K2L11, K2L2);
Z1_q_a[7]_PORT_A_data_in_reg = DFFE(Z1_q_a[7]_PORT_A_data_in, Z1_q_a[7]_clock_0, , , );
Z1_q_a[7]_PORT_A_address = BUS(B5_19, B5_18, B5_17, B5_16, B5_15, B5_14, B5_13, B5_12);
Z1_q_a[7]_PORT_A_address_reg = DFFE(Z1_q_a[7]_PORT_A_address, Z1_q_a[7]_clock_0, , , );
Z1_q_a[7]_PORT_A_write_enable = 70;
Z1_q_a[7]_PORT_A_write_enable_reg = DFFE(Z1_q_a[7]_PORT_A_write_enable, Z1_q_a[7]_clock_0, , , );
Z1_q_a[7]_clock_0 = GLOBAL(CLK);
Z1_q_a[7]_PORT_A_data_out = MEMORY(Z1_q_a[7]_PORT_A_data_in_reg, , Z1_q_a[7]_PORT_A_address_reg, , Z1_q_a[7]_PORT_A_write_enable_reg, , , , Z1_q_a[7]_clock_0, , , , , );
Z1_q_a[7]_PORT_A_data_out_reg = DFFE(Z1_q_a[7]_PORT_A_data_out, Z1_q_a[7]_clock_0, , , );
Z1_q_a[1] = Z1_q_a[7]_PORT_A_data_out_reg[6];

--Z1_q_a[2] is 8cpu:92|lpm_ram_dq0:inst|altsyncram:altsyncram_component|altsyncram_rs21:auto_generated|q_a[2] at M4K_X17_Y7
Z1_q_a[7]_PORT_A_data_in = BUS(K3L22, K3L91, K3L41, K3L2, K2L12, K2L61, K2L11, K2L2);
Z1_q_a[7]_PORT_A_data_in_reg = DFFE(Z1_q_a[7]_PORT_A_data_in, Z1_q_a[7]_clock_0, , , );
Z1_q_a[7]_PORT_A_address = BUS(B5_19, B5_18, B5_17, B5_16, B5_15, B5_14, B5_13, B5_12);
Z1_q_a[7]_PORT_A_address_reg = DFFE(Z1_q_a[7]_PORT_A_address, Z1_q_a[7]_clock_0, , , );
Z1_q_a[7]_PORT_A_write_enable = 70;
Z1_q_a[7]_PORT_A_write_enable_reg = DFFE(Z1_q_a[7]_PORT_A_write_enable, Z1_q_a[7]_clock_0, , , );
Z1_q_a[7]_clock_0 = GLOBAL(CLK);
Z1_q_a[7]_PORT_A_data_out = MEMORY(Z1_q_a[7]_PORT_A_data_in_reg, , Z1_q_a[7]_PORT_A_address_reg, , Z1_q_a[7]_PORT_A_write_enable_reg, , , , Z1_q_a[7]_clock_0, , , , , );
Z1_q_a[7]_PORT_A_data_out_reg = DFFE(Z1_q_a[7]_PORT_A_data_out, Z1_q_a[7]_clock_0, , , );
Z1_q_a[2] = Z1_q_a[7]_PORT_A_data_out_reg[5];

--Z1_q_a[3] is 8cpu:92|lpm_ram_dq0:inst|altsyncram:altsyncram_component|altsyncram_rs21:auto_generated|q_a[3] at M4K_X17_Y7
Z1_q_a[7]_PORT_A_data_in = BUS(K3L22, K3L91, K3L41, K3L2, K2L12, K2L61, K2L11, K2L2);
Z1_q_a[7]_PORT_A_data_in_reg = DFFE(Z1_q_a[7]_PORT_A_data_in, Z1_q_a[7]_clock_0, , , );
Z1_q_a[7]_PORT_A_address = BUS(B5_19, B5_18, B5_17, B5_16, B5_15, B5_14, B5_13, B5_12);
Z1_q_a[7]_PORT_A_address_reg = DFFE(Z1_q_a[7]_PORT_A_address, Z1_q_a[7]_clock_0, , , );
Z1_q_a[7]_PORT_A_write_enable = 70;
Z1_q_a[7]_PORT_A_write_enable_reg = DFFE(Z1_q_a[7]_PORT_A_write_enable, Z1_q_a[7]_clock_0, , , );
Z1_q_a[7]_clock_0 = GLOBAL(CLK);
Z1_q_a[7]_PORT_A_data_out = MEMORY(Z1_q_a[7]_PORT_A_data_in_reg, , Z1_q_a[7]_PORT_A_address_reg, , Z1_q_a[7]_PORT_A_write_enable_reg, , , , Z1_q_a[7]_clock_0, , , , , );
Z1_q_a[7]_PORT_A_data_out_reg = DFFE(Z1_q_a[7]_PORT_A_data_out, Z1_q_a[7]_clock_0, , , );
Z1_q_a[3] = Z1_q_a[7]_PORT_A_data_out_reg[4];

--Z1_q_a[4] is 8cpu:92|lpm_ram_dq0:inst|altsyncram:altsyncram_component|altsyncram_rs21:auto_generated|q_a[4] at M4K_X17_Y7
Z1_q_a[7]_PORT_A_data_in = BUS(K3L22, K3L91, K3L41, K3L2, K2L12, K2L61, K2L11, K2L2);
Z1_q_a[7]_PORT_A_data_in_reg = DFFE(Z1_q_a[7]_PORT_A_data_in, Z1_q_a[7]_clock_0, , , );
Z1_q_a[7]_PORT_A_address = BUS(B5_19, B5_18, B5_17, B5_16, B5_15, B5_14, B5_13, B5_12);
Z1_q_a[7]_PORT_A_address_reg = DFFE(Z1_q_a[7]_PORT_A_address, Z1_q_a[7]_clock_0, , , );
Z1_q_a[7]_PORT_A_write_enable = 70;
Z1_q_a[7]_PORT_A_write_enable_reg = DFFE(Z1_q_a[7]_PORT_A_write_enable, Z1_q_a[7]_clock_0, , , );
Z1_q_a[7]_clock_0 = GLOBAL(CLK);
Z1_q_a[7]_PORT_A_data_out = MEMORY(Z1_q_a[7]_PORT_A_data_in_reg, , Z1_q_a[7]_PORT_A_address_reg, , Z1_q_a[7]_PORT_A_write_enable_reg, , , , Z1_q_a[7]_clock_0, , , , , );
Z1_q_a[7]_PORT_A_data_out_reg = DFFE(Z1_q_a[7]_PORT_A_data_out, Z1_q_a[7]_clock_0, , , );
Z1_q_a[4] = Z1_q_a[7]_PORT_A_data_out_reg[3];

--Z1_q_a[5] is 8cpu:92|lpm_ram_dq0:inst|altsyncram:altsyncram_component|altsyncram_rs21:auto_generated|q_a[5] at M4K_X17_Y7
Z1_q_a[7]_PORT_A_data_in = BUS(K3L22, K3L91, K3L41, K3L2, K2L12, K2L61, K2L11, K2L2);
Z1_q_a[7]_PORT_A_data_in_reg = DFFE(Z1_q_a[7]_PORT_A_data_in, Z1_q_a[7]_clock_0, , , );
Z1_q_a[7]_PORT_A_address = BUS(B5_19, B5_18, B5_17, B5_16, B5_15, B5_14, B5_13, B5_12);
Z1_q_a[7]_PORT_A_address_reg = DFFE(Z1_q_a[7]_PORT_A_address, Z1_q_a[7]_clock_0, , , );
Z1_q_a[7]_PORT_A_write_enable = 70;
Z1_q_a[7]_PORT_A_write_enable_reg = DFFE(Z1_q_a[7]_PORT_A_write_enable, Z1_q_a[7]_clock_0, , , );
Z1_q_a[7]_clock_0 = GLOBAL(CLK);
Z1_q_a[7]_PORT_A_data_out = MEMORY(Z1_q_a[7]_PORT_A_data_in_reg, , Z1_q_a[7]_PORT_A_address_reg, , Z1_q_a[7]_PORT_A_write_enable_reg, , , , Z1_q_a[7]_clock_0, , , , , );
Z1_q_a[7]_PORT_A_data_out_reg = DFFE(Z1_q_a[7]_PORT_A_data_out, Z1_q_a[7]_clock_0, , , );
Z1_q_a[5] = Z1_q_a[7]_PORT_A_data_out_reg[2];

--Z1_q_a[6] is 8cpu:92|lpm_ram_dq0:inst|altsyncram:altsyncram_component|altsyncram_rs21:auto_generated|q_a[6] at M4K_X17_Y7
Z1_q_a[7]_PORT_A_data_in = BUS(K3L22, K3L91, K3L41, K3L2, K2L12, K2L61, K2L11, K2L2);
Z1_q_a[7]_PORT_A_data_in_reg = DFFE(Z1_q_a[7]_PORT_A_data_in, Z1_q_a[7]_clock_0, , , );
Z1_q_a[7]_PORT_A_address = BUS(B5_19, B5_18, B5_17, B5_16, B5_15, B5_14, B5_13, B5_12);
Z1_q_a[7]_PORT_A_address_reg = DFFE(Z1_q_a[7]_PORT_A_address, Z1_q_a[7]_clock_0, , , );
Z1_q_a[7]_PORT_A_write_enable = 70;
Z1_q_a[7]_PORT_A_write_enable_reg = DFFE(Z1_q_a[7]_PORT_A_write_enable, Z1_q_a[7]_clock_0, , , );
Z1_q_a[7]_clock_0 = GLOBAL(CLK);
Z1_q_a[7]_PORT_A_data_out = MEMORY(Z1_q_a[7]_PORT_A_data_in_reg, , Z1_q_a[7]_PORT_A_address_reg, , Z1_q_a[7]_PORT_A_write_enable_reg, , , , Z1_q_a[7]_clock_0, , , , , );
Z1_q_a[7]_PORT_A_data_out_reg = DFFE(Z1_q_a[7]_PORT_A_data_out, Z1_q_a[7]_clock_0, , , );
Z1_q_a[6] = Z1_q_a[7]_PORT_A_data_out_reg[1];


--S4L71 is 8cpu:92|busmux:49|lpm_mux:$00000|mux_afc:auto_generated|w_result97w~88 at LC_X24_Y6_N7
--operation mode is normal

B9_12_qfbk = B9_12;
S4L71 = S4L61 & (S4L51 # B9_12_qfbk) # !S4L61 & !S4L51 & (Z1_q_a[7]);

--B9_12 is 8cpu:92|alu:62|74273b:11|12 at LC_X24_Y6_N7
--operation mode is normal

B9_12 = DFFEAS(S4L71, M1_22, VCC, , , W3L2, , , VCC);


--S4L81 is 8cpu:92|busmux:49|lpm_mux:$00000|mux_afc:auto_generated|w_result97w~89 at LC_X20_Y7_N6
--operation mode is normal

S4L81 = S4L51 & (S4L71 & kdata[8] # !S4L71 & (X1L82)) # !S4L51 & (S4L71);


--S4L91 is 8cpu:92|busmux:49|lpm_mux:$00000|mux_afc:auto_generated|w_result97w~90 at LC_X24_Y6_N5
--operation mode is normal

B1_14_qfbk = B1_14;
S4L91 = H1_33 & (B1_14_qfbk & B1_15);

--B1_14 is 74273b:2|14 at LC_X24_Y6_N5
--operation mode is normal

B1_14 = DFFEAS(S4L91, GLOBAL(39), CLRN, , , BB1_q_a[21], , , VCC);


--X1L52 is 8cpu:92|bi74670:67|74670c:32|121~11 at LC_X21_Y7_N5
--operation mode is normal

X1L52 = 68 & (X1_66 # 69) # !68 & (!69 & X1_56);


--X1L62 is 8cpu:92|bi74670:67|74670c:32|121~12 at LC_X21_Y7_N2
--operation mode is normal

X1L62 = X1L52 & (X1_75 # !69) # !X1L52 & (69 & X1_65);


--S4L31 is 8cpu:92|busmux:49|lpm_mux:$00000|mux_afc:auto_generated|w_result85w~16 at LC_X21_Y7_N8
--operation mode is normal

S4L31 = S4L61 & (S4L51) # !S4L61 & (S4L51 & X1L62 # !S4L51 & (Z1_q_a[6]));


--S4L41 is 8cpu:92|busmux:49|lpm_mux:$00000|mux_afc:auto_generated|w_result85w~17 at LC_X21_Y6_N9
--operation mode is normal

B9_13_qfbk = B9_13;
S4L41 = S4L61 & (S4L31 & kdata[7] # !S4L31 & (B9_13_qfbk)) # !S4L61 & (S4L31);

--B9_13 is 8cpu:92|alu:62|74273b:11|13 at LC_X21_Y6_N9
--operation mode is normal

B9_13 = DFFEAS(S4L41, M1_22, VCC, , , W3L5, , , VCC);


--K3L61 is 8cpu:92|pc:65|74161:9|f74161:sub|95~0 at LC_X20_Y7_N3
--operation mode is arithmetic

K3L61 = K3_99 $ (K3L9 & K3_85);

--K3_95 is 8cpu:92|pc:65|74161:9|f74161:sub|95 at LC_X20_Y7_N3
--operation mode is arithmetic

K3_95_cout_0 = !K3_85 # !K3_99;
K3_95 = CARRY(K3_95_cout_0);

--K3L71 is 8cpu:92|pc:65|74161:9|f74161:sub|95~COUT1_2 at LC_X20_Y7_N3
--operation mode is arithmetic

K3L71_cout_1 = !K3L21 # !K3_99;
K3L71 = CARRY(K3L71_cout_1);


--X1L32 is 8cpu:92|bi74670:67|74670c:32|112~11 at LC_X20_Y8_N7
--operation mode is normal

X1L32 = 68 & (69) # !68 & (69 & (X1_40) # !69 & X1_51);


--X1L42 is 8cpu:92|bi74670:67|74670c:32|112~12 at LC_X20_Y6_N5
--operation mode is normal

X1L42 = 68 & (X1L32 & (X1_30) # !X1L32 & X1_39) # !68 & (X1L32);


--S4L11 is 8cpu:92|busmux:49|lpm_mux:$00000|mux_afc:auto_generated|w_result73w~16 at LC_X24_Y6_N3
--operation mode is normal

B9_14_qfbk = B9_14;
S4L11 = S4L61 & (S4L51 # B9_14_qfbk) # !S4L61 & !S4L51 & (Z1_q_a[5]);

--B9_14 is 8cpu:92|alu:62|74273b:11|14 at LC_X24_Y6_N3
--operation mode is normal

B9_14 = DFFEAS(S4L11, M1_22, VCC, , , W3L8, , , VCC);


--S4L21 is 8cpu:92|busmux:49|lpm_mux:$00000|mux_afc:auto_generated|w_result73w~17 at LC_X20_Y6_N9
--operation mode is normal

S4L21 = S4L51 & (S4L11 & kdata[6] # !S4L11 & (X1L42)) # !S4L51 & S4L11;


--K3L11 is 8cpu:92|pc:65|74161:9|f74161:sub|85~0 at LC_X20_Y7_N2
--operation mode is arithmetic

K3L11 = K3_87 $ (K3L9 & !K3_81);

--K3_85 is 8cpu:92|pc:65|74161:9|f74161:sub|85 at LC_X20_Y7_N2
--operation mode is arithmetic

K3_85_cout_0 = K3_87 & (!K3_81);
K3_85 = CARRY(K3_85_cout_0);

--K3L21 is 8cpu:92|pc:65|74161:9|f74161:sub|85~COUT1_2 at LC_X20_Y7_N2
--operation mode is arithmetic

K3L21_cout_1 = K3_87 & (!K3L5);
K3L21 = CARRY(K3L21_cout_1);


--X1L12 is 8cpu:92|bi74670:67|74670c:32|107~11 at LC_X19_Y7_N7
--operation mode is normal

X1L12 = 69 & (68) # !69 & (68 & (X1_20) # !68 & X1_5);


--X1L22 is 8cpu:92|bi74670:67|74670c:32|107~12 at LC_X19_Y7_N5
--operation mode is normal

X1L22 = X1L12 & (X1_29 # !69) # !X1L12 & 69 & (X1_19);


--S4L9 is 8cpu:92|busmux:49|lpm_mux:$00000|mux_afc:auto_generated|w_result61w~16 at LC_X19_Y7_N2
--operation mode is normal

S4L9 = S4L51 & (X1L22 # S4L61) # !S4L51 & Z1_q_a[4] & (!S4L61);


--S4L01 is 8cpu:92|busmux:49|lpm_mux:$00000|mux_afc:auto_generated|w_result61w~17 at LC_X24_Y6_N0
--operation mode is normal

B9_15_qfbk = B9_15;
S4L01 = S4L61 & (S4L9 & kdata[5] # !S4L9 & (B9_15_qfbk)) # !S4L61 & (S4L9);

--B9_15 is 8cpu:92|alu:62|74273b:11|15 at LC_X24_Y6_N0
--operation mode is normal

B9_15 = DFFEAS(S4L01, M1_22, VCC, , , W3L11, , , VCC);


--K3L4 is 8cpu:92|pc:65|74161:9|f74161:sub|81~0 at LC_X20_Y7_N1
--operation mode is arithmetic

K3L4 = K3_9 $ (K3L7);

--K3_81 is 8cpu:92|pc:65|74161:9|f74161:sub|81 at LC_X20_Y7_N1
--operation mode is arithmetic

K3_81_cout_0 = !K3L7 # !K3_9;
K3_81 = CARRY(K3_81_cout_0);

--K3L5 is 8cpu:92|pc:65|74161:9|f74161:sub|81~COUT1 at LC_X20_Y7_N1
--operation mode is arithmetic

K3L5_cout_1 = !K3L8 # !K3_9;
K3L5 = CARRY(K3L5_cout_1);


--X2L32 is 8cpu:92|bi74670:67|74670c:34|126~11 at LC_X19_Y8_N7
--operation mode is normal

X2L32 = 68 & (69) # !68 & (69 & (X2_86) # !69 & X2_95);


--X2L42 is 8cpu:92|bi74670:67|74670c:34|126~12 at LC_X20_Y6_N4
--operation mode is normal

X2L42 = 68 & (X2L32 & (X2_76) # !X2L32 & X2_85) # !68 & (X2L32);


--S4L7 is 8cpu:92|busmux:49|lpm_mux:$00000|mux_afc:auto_generated|w_result49w~16 at LC_X22_Y6_N8
--operation mode is normal

B9_16_qfbk = B9_16;
S4L7 = S4L51 & S4L61 # !S4L51 & (S4L61 & B9_16_qfbk # !S4L61 & (Z1_q_a[3]));

--B9_16 is 8cpu:92|alu:62|74273b:11|16 at LC_X22_Y6_N8
--operation mode is normal

B9_16 = DFFEAS(S4L7, M1_22, VCC, , , W3L51, , , VCC);


--S4L8 is 8cpu:92|busmux:49|lpm_mux:$00000|mux_afc:auto_generated|w_result49w~17 at LC_X22_Y6_N1
--operation mode is normal

S4L8 = S4L51 & (S4L7 & kdata[4] # !S4L7 & (X2L42)) # !S4L51 & (S4L7);


--K2L81 is 8cpu:92|pc:65|74161:8|f74161:sub|105~0 at LC_X21_Y8_N8
--operation mode is arithmetic

K2L81 = K2_110 $ K2_95;

--K2_105 is 8cpu:92|pc:65|74161:8|f74161:sub|105 at LC_X21_Y8_N8
--operation mode is arithmetic

K2_105_cout_0 = !K2_95 # !K2_110;
K2_105 = CARRY(K2_105_cout_0);

--K2L91 is 8cpu:92|pc:65|74161:8|f74161:sub|105~COUT1_2 at LC_X21_Y8_N8
--operation mode is arithmetic

K2L91_cout_1 = !K2L41 # !K2_110;
K2L91 = CARRY(K2L91_cout_1);


--X2L12 is 8cpu:92|bi74670:67|74670c:34|121~11 at LC_X22_Y8_N9
--operation mode is normal

X2L12 = 69 & 68 # !69 & (68 & X2_66 # !68 & (X2_56));


--X2L22 is 8cpu:92|bi74670:67|74670c:34|121~12 at LC_X22_Y8_N5
--operation mode is normal

X2L22 = 69 & (X2L12 & (X2_75) # !X2L12 & X2_65) # !69 & (X2L12);


--S4L5 is 8cpu:92|busmux:49|lpm_mux:$00000|mux_afc:auto_generated|w_result37w~16 at LC_X22_Y8_N8
--operation mode is normal

S4L5 = S4L61 & (S4L51) # !S4L61 & (S4L51 & X2L22 # !S4L51 & (Z1_q_a[2]));


--S4L6 is 8cpu:92|busmux:49|lpm_mux:$00000|mux_afc:auto_generated|w_result37w~17 at LC_X22_Y8_N4
--operation mode is normal

B9_17_qfbk = B9_17;
S4L6 = S4L61 & (S4L5 & (kdata[3]) # !S4L5 & B9_17_qfbk) # !S4L61 & S4L5;

--B9_17 is 8cpu:92|alu:62|74273b:11|17 at LC_X22_Y8_N4
--operation mode is normal

B9_17 = DFFEAS(S4L6, M1_22, VCC, , , W3L81, , , VCC);


--K2L31 is 8cpu:92|pc:65|74161:8|f74161:sub|95~0 at LC_X21_Y8_N7
--operation mode is arithmetic

K2L31 = K2_99 $ (!K2_85);

--K2_95 is 8cpu:92|pc:65|74161:8|f74161:sub|95 at LC_X21_Y8_N7
--operation mode is arithmetic

K2_95_cout_0 = K2_99 & (!K2_85);
K2_95 = CARRY(K2_95_cout_0);

--K2L41 is 8cpu:92|pc:65|74161:8|f74161:sub|95~COUT1_2 at LC_X21_Y8_N7
--operation mode is arithmetic

K2L41_cout_1 = K2_99 & (!K2L9);
K2L41 = CARRY(K2L41_cout_1);


--X2L91 is 8cpu:92|bi74670:67|74670c:34|112~11 at LC_X20_Y8_N8
--operation mode is normal

X2L91 = 69 & (X2_40 # 68) # !69 & (!68 & X2_51);


--X2L02 is 8cpu:92|bi74670:67|74670c:34|112~12 at LC_X20_Y8_N2