mycpu.fit.eqn

Quartus II 5.0下写的一个单总线架构的CPU设计

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--W3L1 is 8cpu:92|alu:62|lpm_add_sub:1|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~151 at LC_X21_Y6_N8
--operation mode is normal

W3L1_carry_eqn = (!W3L21 & W3L3) # (W3L21 & W3L4);
W3L1 = !W3L1_carry_eqn;


--AB1_9 is sequence:103|74393b:25|9 at LC_X23_Y6_N3
--operation mode is normal

AB1_9_lut_out = !AB1_9;
AB1_9 = DFFEAS(AB1_9_lut_out, !GLOBAL(CLK), F1_11, , AB1_11, , , , );


--AB1_3 is sequence:103|74393b:25|3 at LC_X23_Y6_N2
--operation mode is normal

AB1_3_lut_out = !AB1_3;
AB1_3 = DFFEAS(AB1_3_lut_out, !GLOBAL(CLK), F1_11, , AB1_1, , , , );


--AB1_1 is sequence:103|74393b:25|1 at LC_X25_Y6_N2
--operation mode is normal

AB1_1_lut_out = !AB1_1;
AB1_1 = DFFEAS(AB1_1_lut_out, !GLOBAL(CLK), F1_11, , , , , , );


--AB1_5 is sequence:103|74393b:25|5 at LC_X25_Y6_N4
--operation mode is normal

AB1_5_lut_out = !AB1_5;
AB1_5 = DFFEAS(AB1_5_lut_out, !GLOBAL(CLK), F1_11, , AB1L4, , , , );


--H1_33 is sequence:103|33 at LC_X24_Y6_N9
--operation mode is normal

H1_33 = AB1_9 & AB1_3 & !AB1_1 & !AB1_5;


--H1_28 is sequence:103|28 at LC_X24_Y6_N8
--operation mode is normal

H1_28 = !AB1_9 & AB1_3 & !AB1_1 & !AB1_5;


--H1_35 is sequence:103|35 at LC_X22_Y6_N6
--operation mode is normal

H1_35 = AB1_9 & !AB1_1 & AB1_5 & !AB1_3;


--97 is 97 at LC_X22_Y6_N9
--operation mode is normal

B2_14_qfbk = B2_14;
97 = H1_35 & (B4_18 # B2_14_qfbk) # !CLRN;

--B2_14 is 74273b:3|14 at LC_X22_Y6_N9
--operation mode is normal

B2_14 = DFFEAS(97, GLOBAL(39), CLRN, , , BB1_q_a[13], , , VCC);


--H1_37 is sequence:103|37 at LC_X22_Y6_N2
--operation mode is normal

H1_37 = !AB1_9 & !AB1_1 & AB1_5 & !AB1_3;


--B6_12 is 8cpu:92|74273b:7|12 at LC_X20_Y7_N9
--operation mode is normal

B6_12_lut_out = K3L22;
B6_12 = DFFEAS(B6_12_lut_out, GLOBAL(G1_12), VCC, , , , , , );


--B6_13 is 8cpu:92|74273b:7|13 at LC_X20_Y7_N5
--operation mode is normal

B6_13_lut_out = K3L91;
B6_13 = DFFEAS(B6_13_lut_out, GLOBAL(G1_12), VCC, , , , , , );


--B6_14 is 8cpu:92|74273b:7|14 at LC_X20_Y10_N2
--operation mode is normal

B6_14_lut_out = K3L41;
B6_14 = DFFEAS(B6_14_lut_out, GLOBAL(G1_12), VCC, , , , , , );


--B6_15 is 8cpu:92|74273b:7|15 at LC_X15_Y7_N2
--operation mode is normal

B6_15_lut_out = GND;
B6_15 = DFFEAS(B6_15_lut_out, GLOBAL(G1_12), VCC, , , K3L2, , , VCC);


--B6_16 is 8cpu:92|74273b:7|16 at LC_X19_Y8_N4
--operation mode is normal

B6_16_lut_out = K2L12;
B6_16 = DFFEAS(B6_16_lut_out, GLOBAL(G1_12), VCC, , , , , , );


--B6_17 is 8cpu:92|74273b:7|17 at LC_X21_Y8_N1
--operation mode is normal

B6_17_lut_out = K2L61;
B6_17 = DFFEAS(B6_17_lut_out, GLOBAL(G1_12), VCC, , , , , , );


--B6_18 is 8cpu:92|74273b:7|18 at LC_X20_Y8_N9
--operation mode is normal

B6_18_lut_out = K2L11;
B6_18 = DFFEAS(B6_18_lut_out, GLOBAL(G1_12), VCC, , , , , , );


--B6_19 is 8cpu:92|74273b:7|19 at LC_X21_Y8_N4
--operation mode is normal

B6_19_lut_out = K2L2;
B6_19 = DFFEAS(B6_19_lut_out, GLOBAL(G1_12), VCC, , , , , , );


--B1_12 is 74273b:2|12 at LC_X24_Y6_N1
--operation mode is normal

B1_12_lut_out = BB1_q_a[23];
B1_12 = DFFEAS(B1_12_lut_out, GLOBAL(39), CLRN, , , , , , );


--B2_15 is 74273b:3|15 at LC_X19_Y5_N3
--operation mode is normal

B2_15_lut_out = BB1_q_a[12];
B2_15 = DFFEAS(B2_15_lut_out, GLOBAL(39), CLRN, , , , , , );


--B2_16 is 74273b:3|16 at LC_X19_Y5_N8
--operation mode is normal

B2_16_lut_out = BB1_q_a[11];
B2_16 = DFFEAS(B2_16_lut_out, GLOBAL(39), CLRN, , , , , , );


--B4_12 is 74273b:21|12 at LC_X19_Y5_N7
--operation mode is normal

B4_12_lut_out = BB1_q_a[7];
B4_12 = DFFEAS(B4_12_lut_out, GLOBAL(39), CLRN, , , , , , );


--B4_13 is 74273b:21|13 at LC_X19_Y5_N5
--operation mode is normal

B4_13_lut_out = GND;
B4_13 = DFFEAS(B4_13_lut_out, GLOBAL(39), CLRN, , , BB1_q_a[6], , , VCC);


--B4_14 is 74273b:21|14 at LC_X19_Y5_N4
--operation mode is normal

B4_14_lut_out = GND;
B4_14 = DFFEAS(B4_14_lut_out, GLOBAL(39), CLRN, , , BB1_q_a[5], , , VCC);


--B4_15 is 74273b:21|15 at LC_X19_Y5_N6
--operation mode is normal

B4_15_lut_out = GND;
B4_15 = DFFEAS(B4_15_lut_out, GLOBAL(39), CLRN, , , BB1_q_a[4], , , VCC);


--B4_16 is 74273b:21|16 at LC_X19_Y5_N2
--operation mode is normal

B4_16_lut_out = GND;
B4_16 = DFFEAS(B4_16_lut_out, GLOBAL(39), CLRN, , , BB1_q_a[3], , , VCC);


--B4_17 is 74273b:21|17 at LC_X19_Y5_N9
--operation mode is normal

B4_17_lut_out = BB1_q_a[2];
B4_17 = DFFEAS(B4_17_lut_out, GLOBAL(39), CLRN, , , , , , );


--BB1_q_a[23] is lpm_rom6:inst2|altsyncram:altsyncram_component|altsyncram_3mp:auto_generated|q_a[23] at M4K_X17_Y5
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 18
--Port A Logical Depth: 256, Port A Logical Width: 24
--Port A Input: Registered, Port A Output: Registered
BB1_q_a[23]_PORT_A_address = BUS(K1_9, K1_87, K1_99, K1_110, B3_15, B3_14, 24, 25);
BB1_q_a[23]_PORT_A_address_reg = DFFE(BB1_q_a[23]_PORT_A_address, BB1_q_a[23]_clock_0, , , );
BB1_q_a[23]_clock_0 = GLOBAL(CLK);
BB1_q_a[23]_PORT_A_data_out = MEMORY(, , BB1_q_a[23]_PORT_A_address_reg, , , , , , BB1_q_a[23]_clock_0, , , , , );
BB1_q_a[23]_PORT_A_data_out_reg = DFFE(BB1_q_a[23]_PORT_A_data_out, BB1_q_a[23]_clock_0, , , );
BB1_q_a[23] = BB1_q_a[23]_PORT_A_data_out_reg[0];

--BB1_q_a[2] is lpm_rom6:inst2|altsyncram:altsyncram_component|altsyncram_3mp:auto_generated|q_a[2] at M4K_X17_Y5
BB1_q_a[23]_PORT_A_address = BUS(K1_9, K1_87, K1_99, K1_110, B3_15, B3_14, 24, 25);
BB1_q_a[23]_PORT_A_address_reg = DFFE(BB1_q_a[23]_PORT_A_address, BB1_q_a[23]_clock_0, , , );
BB1_q_a[23]_clock_0 = GLOBAL(CLK);
BB1_q_a[23]_PORT_A_data_out = MEMORY(, , BB1_q_a[23]_PORT_A_address_reg, , , , , , BB1_q_a[23]_clock_0, , , , , );
BB1_q_a[23]_PORT_A_data_out_reg = DFFE(BB1_q_a[23]_PORT_A_data_out, BB1_q_a[23]_clock_0, , , );
BB1_q_a[2] = BB1_q_a[23]_PORT_A_data_out_reg[17];

--BB1_q_a[3] is lpm_rom6:inst2|altsyncram:altsyncram_component|altsyncram_3mp:auto_generated|q_a[3] at M4K_X17_Y5
BB1_q_a[23]_PORT_A_address = BUS(K1_9, K1_87, K1_99, K1_110, B3_15, B3_14, 24, 25);
BB1_q_a[23]_PORT_A_address_reg = DFFE(BB1_q_a[23]_PORT_A_address, BB1_q_a[23]_clock_0, , , );
BB1_q_a[23]_clock_0 = GLOBAL(CLK);
BB1_q_a[23]_PORT_A_data_out = MEMORY(, , BB1_q_a[23]_PORT_A_address_reg, , , , , , BB1_q_a[23]_clock_0, , , , , );
BB1_q_a[23]_PORT_A_data_out_reg = DFFE(BB1_q_a[23]_PORT_A_data_out, BB1_q_a[23]_clock_0, , , );
BB1_q_a[3] = BB1_q_a[23]_PORT_A_data_out_reg[16];

--BB1_q_a[4] is lpm_rom6:inst2|altsyncram:altsyncram_component|altsyncram_3mp:auto_generated|q_a[4] at M4K_X17_Y5
BB1_q_a[23]_PORT_A_address = BUS(K1_9, K1_87, K1_99, K1_110, B3_15, B3_14, 24, 25);
BB1_q_a[23]_PORT_A_address_reg = DFFE(BB1_q_a[23]_PORT_A_address, BB1_q_a[23]_clock_0, , , );
BB1_q_a[23]_clock_0 = GLOBAL(CLK);
BB1_q_a[23]_PORT_A_data_out = MEMORY(, , BB1_q_a[23]_PORT_A_address_reg, , , , , , BB1_q_a[23]_clock_0, , , , , );
BB1_q_a[23]_PORT_A_data_out_reg = DFFE(BB1_q_a[23]_PORT_A_data_out, BB1_q_a[23]_clock_0, , , );
BB1_q_a[4] = BB1_q_a[23]_PORT_A_data_out_reg[15];

--BB1_q_a[5] is lpm_rom6:inst2|altsyncram:altsyncram_component|altsyncram_3mp:auto_generated|q_a[5] at M4K_X17_Y5
BB1_q_a[23]_PORT_A_address = BUS(K1_9, K1_87, K1_99, K1_110, B3_15, B3_14, 24, 25);
BB1_q_a[23]_PORT_A_address_reg = DFFE(BB1_q_a[23]_PORT_A_address, BB1_q_a[23]_clock_0, , , );
BB1_q_a[23]_clock_0 = GLOBAL(CLK);
BB1_q_a[23]_PORT_A_data_out = MEMORY(, , BB1_q_a[23]_PORT_A_address_reg, , , , , , BB1_q_a[23]_clock_0, , , , , );
BB1_q_a[23]_PORT_A_data_out_reg = DFFE(BB1_q_a[23]_PORT_A_data_out, BB1_q_a[23]_clock_0, , , );
BB1_q_a[5] = BB1_q_a[23]_PORT_A_data_out_reg[14];

--BB1_q_a[6] is lpm_rom6:inst2|altsyncram:altsyncram_component|altsyncram_3mp:auto_generated|q_a[6] at M4K_X17_Y5
BB1_q_a[23]_PORT_A_address = BUS(K1_9, K1_87, K1_99, K1_110, B3_15, B3_14, 24, 25);
BB1_q_a[23]_PORT_A_address_reg = DFFE(BB1_q_a[23]_PORT_A_address, BB1_q_a[23]_clock_0, , , );
BB1_q_a[23]_clock_0 = GLOBAL(CLK);
BB1_q_a[23]_PORT_A_data_out = MEMORY(, , BB1_q_a[23]_PORT_A_address_reg, , , , , , BB1_q_a[23]_clock_0, , , , , );
BB1_q_a[23]_PORT_A_data_out_reg = DFFE(BB1_q_a[23]_PORT_A_data_out, BB1_q_a[23]_clock_0, , , );
BB1_q_a[6] = BB1_q_a[23]_PORT_A_data_out_reg[13];

--BB1_q_a[7] is lpm_rom6:inst2|altsyncram:altsyncram_component|altsyncram_3mp:auto_generated|q_a[7] at M4K_X17_Y5
BB1_q_a[23]_PORT_A_address = BUS(K1_9, K1_87, K1_99, K1_110, B3_15, B3_14, 24, 25);
BB1_q_a[23]_PORT_A_address_reg = DFFE(BB1_q_a[23]_PORT_A_address, BB1_q_a[23]_clock_0, , , );
BB1_q_a[23]_clock_0 = GLOBAL(CLK);
BB1_q_a[23]_PORT_A_data_out = MEMORY(, , BB1_q_a[23]_PORT_A_address_reg, , , , , , BB1_q_a[23]_clock_0, , , , , );
BB1_q_a[23]_PORT_A_data_out_reg = DFFE(BB1_q_a[23]_PORT_A_data_out, BB1_q_a[23]_clock_0, , , );
BB1_q_a[7] = BB1_q_a[23]_PORT_A_data_out_reg[12];

--BB1_q_a[9] is lpm_rom6:inst2|altsyncram:altsyncram_component|altsyncram_3mp:auto_generated|q_a[9] at M4K_X17_Y5
BB1_q_a[23]_PORT_A_address = BUS(K1_9, K1_87, K1_99, K1_110, B3_15, B3_14, 24, 25);
BB1_q_a[23]_PORT_A_address_reg = DFFE(BB1_q_a[23]_PORT_A_address, BB1_q_a[23]_clock_0, , , );
BB1_q_a[23]_clock_0 = GLOBAL(CLK);
BB1_q_a[23]_PORT_A_data_out = MEMORY(, , BB1_q_a[23]_PORT_A_address_reg, , , , , , BB1_q_a[23]_clock_0, , , , , );
BB1_q_a[23]_PORT_A_data_out_reg = DFFE(BB1_q_a[23]_PORT_A_data_out, BB1_q_a[23]_clock_0, , , );
BB1_q_a[9] = BB1_q_a[23]_PORT_A_data_out_reg[11];

--BB1_q_a[10] is lpm_rom6:inst2|altsyncram:altsyncram_component|altsyncram_3mp:auto_generated|q_a[10] at M4K_X17_Y5
BB1_q_a[23]_PORT_A_address = BUS(K1_9, K1_87, K1_99, K1_110, B3_15, B3_14, 24, 25);
BB1_q_a[23]_PORT_A_address_reg = DFFE(BB1_q_a[23]_PORT_A_address, BB1_q_a[23]_clock_0, , , );
BB1_q_a[23]_clock_0 = GLOBAL(CLK);
BB1_q_a[23]_PORT_A_data_out = MEMORY(, , BB1_q_a[23]_PORT_A_address_reg, , , , , , BB1_q_a[23]_clock_0, , , , , );
BB1_q_a[23]_PORT_A_data_out_reg = DFFE(BB1_q_a[23]_PORT_A_data_out, BB1_q_a[23]_clock_0, , , );
BB1_q_a[10] = BB1_q_a[23]_PORT_A_data_out_reg[10];

--BB1_q_a[11] is lpm_rom6:inst2|altsyncram:altsyncram_component|altsyncram_3mp:auto_generated|q_a[11] at M4K_X17_Y5
BB1_q_a[23]_PORT_A_address = BUS(K1_9, K1_87, K1_99, K1_110, B3_15, B3_14, 24, 25);
BB1_q_a[23]_PORT_A_address_reg = DFFE(BB1_q_a[23]_PORT_A_address, BB1_q_a[23]_clock_0, , , );
BB1_q_a[23]_clock_0 = GLOBAL(CLK);
BB1_q_a[23]_PORT_A_data_out = MEMORY(, , BB1_q_a[23]_PORT_A_address_reg, , , , , , BB1_q_a[23]_clock_0, , , , , );
BB1_q_a[23]_PORT_A_data_out_reg = DFFE(BB1_q_a[23]_PORT_A_data_out, BB1_q_a[23]_clock_0, , , );
BB1_q_a[11] = BB1_q_a[23]_PORT_A_data_out_reg[9];

--BB1_q_a[12] is lpm_rom6:inst2|altsyncram:altsyncram_component|altsyncram_3mp:auto_generated|q_a[12] at M4K_X17_Y5
BB1_q_a[23]_PORT_A_address = BUS(K1_9, K1_87, K1_99, K1_110, B3_15, B3_14, 24, 25);
BB1_q_a[23]_PORT_A_address_reg = DFFE(BB1_q_a[23]_PORT_A_address, BB1_q_a[23]_clock_0, , , );
BB1_q_a[23]_clock_0 = GLOBAL(CLK);
BB1_q_a[23]_PORT_A_data_out = MEMORY(, , BB1_q_a[23]_PORT_A_address_reg, , , , , , BB1_q_a[23]_clock_0, , , , , );
BB1_q_a[23]_PORT_A_data_out_reg = DFFE(BB1_q_a[23]_PORT_A_data_out, BB1_q_a[23]_clock_0, , , );
BB1_q_a[12] = BB1_q_a[23]_PORT_A_data_out_reg[8];

--BB1_q_a[14] is lpm_rom6:inst2|altsyncram:altsyncram_component|altsyncram_3mp:auto_generated|q_a[14] at M4K_X17_Y5
BB1_q_a[23]_PORT_A_address = BUS(K1_9, K1_87, K1_99, K1_110, B3_15, B3_14, 24, 25);
BB1_q_a[23]_PORT_A_address_reg = DFFE(BB1_q_a[23]_PORT_A_address, BB1_q_a[23]_clock_0, , , );
BB1_q_a[23]_clock_0 = GLOBAL(CLK);
BB1_q_a[23]_PORT_A_data_out = MEMORY(, , BB1_q_a[23]_PORT_A_address_reg, , , , , , BB1_q_a[23]_clock_0, , , , , );
BB1_q_a[23]_PORT_A_data_out_reg = DFFE(BB1_q_a[23]_PORT_A_data_out, BB1_q_a[23]_clock_0, , , );
BB1_q_a[14] = BB1_q_a[23]_PORT_A_data_out_reg[7];

--BB1_q_a[15] is lpm_rom6:inst2|altsyncram:altsyncram_component|altsyncram_3mp:auto_generated|q_a[15] at M4K_X17_Y5
BB1_q_a[23]_PORT_A_address = BUS(K1_9, K1_87, K1_99, K1_110, B3_15, B3_14, 24, 25);
BB1_q_a[23]_PORT_A_address_reg = DFFE(BB1_q_a[23]_PORT_A_address, BB1_q_a[23]_clock_0, , , );
BB1_q_a[23]_clock_0 = GLOBAL(CLK);
BB1_q_a[23]_PORT_A_data_out = MEMORY(, , BB1_q_a[23]_PORT_A_address_reg, , , , , , BB1_q_a[23]_clock_0, , , , , );
BB1_q_a[23]_PORT_A_data_out_reg = DFFE(BB1_q_a[23]_PORT_A_data_out, BB1_q_a[23]_clock_0, , , );
BB1_q_a[15] = BB1_q_a[23]_PORT_A_data_out_reg[6];

--BB1_q_a[13] is lpm_rom6:inst2|altsyncram:altsyncram_component|altsyncram_3mp:auto_generated|q_a[13] at M4K_X17_Y5
BB1_q_a[23]_PORT_A_address = BUS(K1_9, K1_87, K1_99, K1_110, B3_15, B3_14, 24, 25);
BB1_q_a[23]_PORT_A_address_reg = DFFE(BB1_q_a[23]_PORT_A_address, BB1_q_a[23]_clock_0, , , );
BB1_q_a[23]_clock_0 = GLOBAL(CLK);
BB1_q_a[23]_PORT_A_data_out = MEMORY(, , BB1_q_a[23]_PORT_A_address_reg, , , , , , BB1_q_a[23]_clock_0, , , , , );
BB1_q_a[23]_PORT_A_data_out_reg = DFFE(BB1_q_a[23]_PORT_A_data_out, BB1_q_a[23]_clock_0, , , );
BB1_q_a[13] = BB1_q_a[23]_PORT_A_data_out_reg[5];

--BB1_q_a[17] is lpm_rom6:inst2|altsyncram:altsyncram_component|altsyncram_3mp:auto_generated|q_a[17] at M4K_X17_Y5
BB1_q_a[23]_PORT_A_address = BUS(K1_9, K1_87, K1_99, K1_110, B3_15, B3_14, 24, 25);
BB1_q_a[23]_PORT_A_address_reg = DFFE(BB1_q_a[23]_PORT_A_address, BB1_q_a[23]_clock_0, , , );
BB1_q_a[23]_clock_0 = GLOBAL(CLK);
BB1_q_a[23]_PORT_A_data_out = MEMORY(, , BB1_q_a[23]_PORT_A_address_reg, , , , , , BB1_q_a[23]_clock_0, , , , , );
BB1_q_a[23]_PORT_A_data_out_reg = DFFE(BB1_q_a[23]_PORT_A_data_out, BB1_q_a[23]_clock_0, , , );
BB1_q_a[17] = BB1_q_a[23]_PORT_A_data_out_reg[4];

--BB1_q_a[20] is lpm_rom6:inst2|altsyncram:altsyncram_component|altsyncram_3mp:auto_generated|q_a[20] at M4K_X17_Y5
BB1_q_a[23]_PORT_A_address = BUS(K1_9, K1_87, K1_99, K1_110, B3_15, B3_14, 24, 25);
BB1_q_a[23]_PORT_A_address_reg = DFFE(BB1_q_a[23]_PORT_A_address, BB1_q_a[23]_clock_0, , , );
BB1_q_a[23]_clock_0 = GLOBAL(CLK);
BB1_q_a[23]_PORT_A_data_out = MEMORY(, , BB1_q_a[23]_PORT_A_address_reg, , , , , , BB1_q_a[23]_clock_0, , , , , );
BB1_q_a[23]_PORT_A_data_out_reg = DFFE(BB1_q_a[23]_PORT_A_data_out, BB1_q_a[23]_clock_0, , , );
BB1_q_a[20] = BB1_q_a[23]_PORT_A_data_out_reg[3];

--BB1_q_a[21] is lpm_rom6:inst2|altsyncram:altsyncram_component|altsyncram_3mp:auto_generated|q_a[21] at M4K_X17_Y5
BB1_q_a[23]_PORT_A_address = BUS(K1_9, K1_87, K1_99, K1_110, B3_15, B3_14, 24, 25);
BB1_q_a[23]_PORT_A_address_reg = DFFE(BB1_q_a[23]_PORT_A_address, BB1_q_a[23]_clock_0, , , );
BB1_q_a[23]_clock_0 = GLOBAL(CLK);
BB1_q_a[23]_PORT_A_data_out = MEMORY(, , BB1_q_a[23]_PORT_A_address_reg, , , , , , BB1_q_a[23]_clock_0, , , , , );
BB1_q_a[23]_PORT_A_data_out_reg = DFFE(BB1_q_a[23]_PORT_A_data_out, BB1_q_a[23]_clock_0, , , );
BB1_q_a[21] = BB1_q_a[23]_PORT_A_data_out_reg[2];

--BB1_q_a[22] is lpm_rom6:inst2|altsyncram:altsyncram_component|altsyncram_3mp:auto_generated|q_a[22] at M4K_X17_Y5
BB1_q_a[23]_PORT_A_address = BUS(K1_9, K1_87, K1_99, K1_110, B3_15, B3_14, 24, 25);
BB1_q_a[23]_PORT_A_address_reg = DFFE(BB1_q_a[23]_PORT_A_address, BB1_q_a[23]_clock_0, , , );
BB1_q_a[23]_clock_0 = GLOBAL(CLK);
BB1_q_a[23]_PORT_A_data_out = MEMORY(, , BB1_q_a[23]_PORT_A_address_reg, , , , , , BB1_q_a[23]_clock_0, , , , , );
BB1_q_a[23]_PORT_A_data_out_reg = DFFE(BB1_q_a[23]_PORT_A_data_out, BB1_q_a[23]_clock_0, , , );
BB1_q_a[22] = BB1_q_a[23]_PORT_A_data_out_reg[1];


--BB1_q_a[19] is lpm_rom6:inst2|altsyncram:altsyncram_component|altsyncram_3mp:auto_generated|q_a[19] at M4K_X17_Y6
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 6
--Port A Logical Depth: 256, Port A Logical Width: 24
--Port A Input: Registered, Port A Output: Registered
BB1_q_a[19]_PORT_A_address = BUS(K1_9, K1_87, K1_99, K1_110, B3_15, B3_14, 24, 25);
BB1_q_a[19]_PORT_A_address_reg = DFFE(BB1_q_a[19]_PORT_A_address, BB1_q_a[19]_clock_0, , , );
BB1_q_a[19]_clock_0 = GLOBAL(CLK);
BB1_q_a[19]_PORT_A_data_out = MEMORY(, , BB1_q_a[19]_PORT_A_address_reg, , , , , , BB1_q_a[19]_clock_0, , , , , );
BB1_q_a[19]_PORT_A_data_out_reg = DFFE(BB1_q_a[19]_PORT_A_data_out, BB1_q_a[19]_clock_0, , , );
BB1_q_a[19] = BB1_q_a[19]_PORT_A_data_out_reg[0];

--BB1_q_a[0] is lpm_rom6:inst2|altsyncram:altsyncram_component|altsyncram_3mp:auto_generated|q_a[0] at M4K_X17_Y6
BB1_q_a[19]_PORT_A_address = BUS(K1_9, K1_87, K1_99, K1_110, B3_15, B3_14, 24, 25);
BB1_q_a[19]_PORT_A_address_reg = DFFE(BB1_q_a[19]_PORT_A_address, BB1_q_a[19]_clock_0, , , );
BB1_q_a[19]_clock_0 = GLOBAL(CLK);
BB1_q_a[19]_PORT_A_data_out = MEMORY(, , BB1_q_a[19]_PORT_A_address_reg, , , , , , BB1_q_a[19]_clock_0, , , , , );
BB1_q_a[19]_PORT_A_data_out_reg = DFFE(BB1_q_a[19]_PORT_A_data_out, BB1_q_a[19]_clock_0, , , );
BB1_q_a[0] = BB1_q_a[19]_PORT_A_data_out_reg[5];

--BB1_q_a[8] is lpm_rom6:inst2|altsyncram:altsyncram_component|altsyncram_3mp:auto_generated|q_a[8] at M4K_X17_Y6
BB1_q_a[19]_PORT_A_address = BUS(K1_9, K1_87, K1_99, K1_110, B3_15, B3_14, 24, 25);
BB1_q_a[19]_PORT_A_address_reg = DFFE(BB1_q_a[19]_PORT_A_address, BB1_q_a[19]_clock_0, , , );
BB1_q_a[19]_clock_0 = GLOBAL(CLK);
BB1_q_a[19]_PORT_A_data_out = MEMORY(, , BB1_q_a[19]_PORT_A_address_reg, , , , , , BB1_q_a[19]_clock_0, , , , , );
BB1_q_a[19]_PORT_A_data_out_reg = DFFE(BB1_q_a[19]_PORT_A_data_out, BB1_q_a[19]_clock_0, , , );
BB1_q_a[8] = BB1_q_a[19]_PORT_A_data_out_reg[4];

--BB1_q_a[1] is lpm_rom6:inst2|altsyncram:altsyncram_component|altsyncram_3mp:auto_generated|q_a[1] at M4K_X17_Y6
BB1_q_a[19]_PORT_A_address = BUS(K1_9, K1_87, K1_99, K1_110, B3_15, B3_14, 24, 25);
BB1_q_a[19]_PORT_A_address_reg = DFFE(BB1_q_a[19]_PORT_A_address, BB1_q_a[19]_clock_0, , , );
BB1_q_a[19]_clock_0 = GLOBAL(CLK);
BB1_q_a[19]_PORT_A_data_out = MEMORY(, , BB1_q_a[19]_PORT_A_address_reg, , , , , , BB1_q_a[19]_clock_0, , , , , );
BB1_q_a[19]_PORT_A_data_out_reg = DFFE(BB1_q_a[19]_PORT_A_data_out, BB1_q_a[19]_clock_0, , , );
BB1_q_a[1] = BB1_q_a[19]_PORT_A_data_out_reg[3];

--BB1_q_a[16] is lpm_rom6:inst2|altsyncram:altsyncram_component|altsyncram_3mp:auto_generated|q_a[16] at M4K_X17_Y6
BB1_q_a[19]_PORT_A_address = BUS(K1_9, K1_87, K1_99, K1_110, B3_15, B3_14, 24, 25);