top1.tan.qmsg

是基于EDA系统上的一24小时制的数字钟设计

{ "Info" "ITDB_FULL_TCO_RESULT" "CLK LED_G s\[1\] 16.266 ns register " "Info: tco from clock \"CLK\" to destination pin \"LED_G\" through register \"s\[1\]\" is 16.266 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.767 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 2.767 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_17 3 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 3; CLK Node = 'CLK'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top1" "UNKNOWN" "V1" "E:/课件/大三1/课程设计/top1/db/top1.quartus_db" { Floorplan "E:/课件/大三1/课程设计/top1/" "" "" { CLK } "NODE_NAME" } "" } } { "display.vhd" "" { Text "E:/课件/大三1/课程设计/top1/display.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.587 ns) + CELL(0.711 ns) 2.767 ns s\[1\] 2 REG LC_X7_Y12_N0 10 " "Info: 2: + IC(0.587 ns) + CELL(0.711 ns) = 2.767 ns; Loc. = LC_X7_Y12_N0; Fanout = 10; REG Node = 's\[1\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top1" "UNKNOWN" "V1" "E:/课件/大三1/课程设计/top1/db/top1.quartus_db" { Floorplan "E:/课件/大三1/课程设计/top1/" "" "1.298 ns" { CLK s[1] } "NODE_NAME" } "" } } { "display.vhd" "" { Text "E:/课件/大三1/课程设计/top1/display.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.79 % ) " "Info: Total cell delay = 2.180 ns ( 78.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.587 ns ( 21.21 % ) " "Info: Total interconnect delay = 0.587 ns ( 21.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top1" "UNKNOWN" "V1" "E:/课件/大三1/课程设计/top1/db/top1.quartus_db" { Floorplan "E:/课件/大三1/课程设计/top1/" "" "2.767 ns" { CLK s[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.767 ns" { CLK CLK~out0 s[1] } { 0.000ns 0.000ns 0.587ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "display.vhd" "" { Text "E:/课件/大三1/课程设计/top1/display.vhd" 42 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "13.275 ns + Longest register pin " "Info: + Longest register to pin delay is 13.275 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns s\[1\] 1 REG LC_X7_Y12_N0 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y12_N0; Fanout = 10; REG Node = 's\[1\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top1" "UNKNOWN" "V1" "E:/课件/大三1/课程设计/top1/db/top1.quartus_db" { Floorplan "E:/课件/大三1/课程设计/top1/" "" "" { s[1] } "NODE_NAME" } "" } } { "display.vhd" "" { Text "E:/课件/大三1/课程设计/top1/display.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.636 ns) + CELL(0.442 ns) 1.078 ns NUM\[0\]~657 2 COMB LC_X7_Y12_N1 7 " "Info: 2: + IC(0.636 ns) + CELL(0.442 ns) = 1.078 ns; Loc. = LC_X7_Y12_N1; Fanout = 7; COMB Node = 'NUM\[0\]~657'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top1" "UNKNOWN" "V1" "E:/课件/大三1/课程设计/top1/db/top1.quartus_db" { Floorplan "E:/课件/大三1/课程设计/top1/" "" "1.078 ns" { s[1] NUM[0]~657 } "NODE_NAME" } "" } } { "display.vhd" "" { Text "E:/课件/大三1/课程设计/top1/display.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.568 ns) + CELL(0.590 ns) 3.236 ns NUM\[3\]~658 3 COMB LC_X9_Y13_N8 1 " "Info: 3: + IC(1.568 ns) + CELL(0.590 ns) = 3.236 ns; Loc. = LC_X9_Y13_N8; Fanout = 1; COMB Node = 'NUM\[3\]~658'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top1" "UNKNOWN" "V1" "E:/课件/大三1/课程设计/top1/db/top1.quartus_db" { Floorplan "E:/课件/大三1/课程设计/top1/" "" "2.158 ns" { NUM[0]~657 NUM[3]~658 } "NODE_NAME" } "" } } { "display.vhd" "" { Text "E:/课件/大三1/课程设计/top1/display.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.399 ns) + CELL(0.442 ns) 4.077 ns NUM\[3\]~659 4 COMB LC_X9_Y13_N2 1 " "Info: 4: + IC(0.399 ns) + CELL(0.442 ns) = 4.077 ns; Loc. = LC_X9_Y13_N2; Fanout = 1; COMB Node = 'NUM\[3\]~659'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top1" "UNKNOWN" "V1" "E:/课件/大三1/课程设计/top1/db/top1.quartus_db" { Floorplan "E:/课件/大三1/课程设计/top1/" "" "0.841 ns" { NUM[3]~658 NUM[3]~659 } "NODE_NAME" } "" } } { "display.vhd" "" { Text "E:/课件/大三1/课程设计/top1/display.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.540 ns) + CELL(0.292 ns) 5.909 ns NUM\[3\]~669 5 COMB LC_X7_Y12_N8 11 " "Info: 5: + IC(1.540 ns) + CELL(0.292 ns) = 5.909 ns; Loc. = LC_X7_Y12_N8; Fanout = 11; COMB Node = 'NUM\[3\]~669'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top1" "UNKNOWN" "V1" "E:/课件/大三1/课程设计/top1/db/top1.quartus_db" { Floorplan "E:/课件/大三1/课程设计/top1/" "" "1.832 ns" { NUM[3]~659 NUM[3]~669 } "NODE_NAME" } "" } } { "display.vhd" "" { Text "E:/课件/大三1/课程设计/top1/display.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.364 ns) + CELL(0.442 ns) 7.715 ns SEG~1428 6 COMB LC_X7_Y10_N4 2 " "Info: 6: + IC(1.364 ns) + CELL(0.442 ns) = 7.715 ns; Loc. = LC_X7_Y10_N4; Fanout = 2; COMB Node = 'SEG~1428'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top1" "UNKNOWN" "V1" "E:/课件/大三1/课程设计/top1/db/top1.quartus_db" { Floorplan "E:/课件/大三1/课程设计/top1/" "" "1.806 ns" { NUM[3]~669 SEG~1428 } "NODE_NAME" } "" } } { "display.vhd" "" { Text "E:/课件/大三1/课程设计/top1/display.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.415 ns) + CELL(0.442 ns) 8.572 ns SEG~1433 7 COMB LC_X7_Y10_N0 1 " "Info: 7: + IC(0.415 ns) + CELL(0.442 ns) = 8.572 ns; Loc. = LC_X7_Y10_N0; Fanout = 1; COMB Node = 'SEG~1433'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top1" "UNKNOWN" "V1" "E:/课件/大三1/课程设计/top1/db/top1.quartus_db" { Floorplan "E:/课件/大三1/课程设计/top1/" "" "0.857 ns" { SEG~1428 SEG~1433 } "NODE_NAME" } "" } } { "display.vhd" "" { Text "E:/课件/大三1/课程设计/top1/display.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.579 ns) + CELL(2.124 ns) 13.275 ns LED_G 8 PIN PIN_31 0 " "Info: 8: + IC(2.579 ns) + CELL(2.124 ns) = 13.275 ns; Loc. = PIN_31; Fanout = 0; PIN Node = 'LED_G'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top1" "UNKNOWN" "V1" "E:/课件/大三1/课程设计/top1/db/top1.quartus_db" { Floorplan "E:/课件/大三1/课程设计/top1/" "" "4.703 ns" { SEG~1433 LED_G } "NODE_NAME" } "" } } { "display.vhd" "" { Text "E:/课件/大三1/课程设计/top1/display.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.774 ns ( 35.96 % ) " "Info: Total cell delay = 4.774 ns ( 35.96 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.501 ns ( 64.04 % ) " "Info: Total interconnect delay = 8.501 ns ( 64.04 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top1" "UNKNOWN" "V1" "E:/课件/大三1/课程设计/top1/db/top1.quartus_db" { Floorplan "E:/课件/大三1/课程设计/top1/" "" "13.275 ns" { s[1] NUM[0]~657 NUM[3]~658 NUM[3]~659 NUM[3]~669 SEG~1428 SEG~1433 LED_G } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "13.275 ns" { s[1] NUM[0]~657 NUM[3]~658 NUM[3]~659 NUM[3]~669 SEG~1428 SEG~1433 LED_G } { 0.000ns 0.636ns 1.568ns 0.399ns 1.540ns 1.364ns 0.415ns 2.579ns } { 0.000ns 0.442ns 0.590ns 0.442ns 0.292ns 0.442ns 0.442ns 2.124ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top1" "UNKNOWN" "V1" "E:/课件/大三1/课程设计/top1/db/top1.quartus_db" { Floorplan "E:/课件/大三1/课程设计/top1/" "" "2.767 ns" { CLK s[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.767 ns" { CLK CLK~out0 s[1] } { 0.000ns 0.000ns 0.587ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top1" "UNKNOWN" "V1" "E:/课件/大三1/课程设计/top1/db/top1.quartus_db" { Floorplan "E:/课件/大三1/课程设计/top1/" "" "13.275 ns" { s[1] NUM[0]~657 NUM[3]~658 NUM[3]~659 NUM[3]~669 SEG~1428 SEG~1433 LED_G } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "13.275 ns" { s[1] NUM[0]~657 NUM[3]~658 NUM[3]~659 NUM[3]~669 SEG~1428 SEG~1433 LED_G } { 0.000ns 0.636ns 1.568ns 0.399ns 1.540ns 1.364ns 0.415ns 2.579ns } { 0.000ns 0.442ns 0.590ns 0.442ns 0.292ns 0.442ns 0.442ns 2.124ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "din2\[2\] LED_G 17.305 ns Longest " "Info: Longest tpd from source pin \"din2\[2\]\" to destination pin \"LED_G\" is 17.305 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns din2\[2\] 1 PIN PIN_51 1 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_51; Fanout = 1; PIN Node = 'din2\[2\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top1" "UNKNOWN" "V1" "E:/课件/大三1/课程设计/top1/db/top1.quartus_db" { Floorplan "E:/课件/大三1/课程设计/top1/" "" "" { din2[2] } "NODE_NAME" } "" } } { "display.vhd" "" { Text "E:/课件/大三1/课程设计/top1/display.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.323 ns) + CELL(0.442 ns) 8.240 ns NUM\[2\]~662 2 COMB LC_X9_Y13_N9 1 " "Info: 2: + IC(6.323 ns) + CELL(0.442 ns) = 8.240 ns; Loc. = LC_X9_Y13_N9; Fanout = 1; COMB Node = 'NUM\[2\]~662'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top1" "UNKNOWN" "V1" "E:/课件/大三1/课程设计/top1/db/top1.quartus_db" { Floorplan "E:/课件/大三1/课程设计/top1/" "" "6.765 ns" { din2[2] NUM[2]~662 } "NODE_NAME" } "" } } { "display.vhd" "" { Text "E:/课件/大三1/课程设计/top1/display.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.522 ns) + CELL(0.292 ns) 10.054 ns NUM\[2\]~670 3 COMB LC_X7_Y12_N3 11 " "Info: 3: + IC(1.522 ns) + CELL(0.292 ns) = 10.054 ns; Loc. = LC_X7_Y12_N3; Fanout = 11; COMB Node = 'NUM\[2\]~670'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top1" "UNKNOWN" "V1" "E:/课件/大三1/课程设计/top1/db/top1.quartus_db" { Floorplan "E:/课件/大三1/课程设计/top1/" "" "1.814 ns" { NUM[2]~662 NUM[2]~670 } "NODE_NAME" } "" } } { "display.vhd" "" { Text "E:/课件/大三1/课程设计/top1/display.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.399 ns) + CELL(0.292 ns) 11.745 ns SEG~1428 4 COMB LC_X7_Y10_N4 2 " "Info: 4: + IC(1.399 ns) + CELL(0.292 ns) = 11.745 ns; Loc. = LC_X7_Y10_N4; Fanout = 2; COMB Node = 'SEG~1428'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top1" "UNKNOWN" "V1" "E:/课件/大三1/课程设计/top1/db/top1.quartus_db" { Floorplan "E:/课件/大三1/课程设计/top1/" "" "1.691 ns" { NUM[2]~670 SEG~1428 } "NODE_NAME" } "" } } { "display.vhd" "" { Text "E:/课件/大三1/课程设计/top1/display.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.415 ns) + CELL(0.442 ns) 12.602 ns SEG~1433 5 COMB LC_X7_Y10_N0 1 " "Info: 5: + IC(0.415 ns) + CELL(0.442 ns) = 12.602 ns; Loc. = LC_X7_Y10_N0; Fanout = 1; COMB Node = 'SEG~1433'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top1" "UNKNOWN" "V1" "E:/课件/大三1/课程设计/top1/db/top1.quartus_db" { Floorplan "E:/课件/大三1/课程设计/top1/" "" "0.857 ns" { SEG~1428 SEG~1433 } "NODE_NAME" } "" } } { "display.vhd" "" { Text "E:/课件/大三1/课程设计/top1/display.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.579 ns) + CELL(2.124 ns) 17.305 ns LED_G 6 PIN PIN_31 0 " "Info: 6: + IC(2.579 ns) + CELL(2.124 ns) = 17.305 ns; Loc. = PIN_31; Fanout = 0; PIN Node = 'LED_G'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top1" "UNKNOWN" "V1" "E:/课件/大三1/课程设计/top1/db/top1.quartus_db" { Floorplan "E:/课件/大三1/课程设计/top1/" "" "4.703 ns" { SEG~1433 LED_G } "NODE_NAME" } "" } } { "display.vhd" "" { Text "E:/课件/大三1/课程设计/top1/display.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.067 ns ( 29.28 % ) " "Info: Total cell delay = 5.067 ns ( 29.28 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "12.238 ns ( 70.72 % ) " "Info: Total interconnect delay = 12.238 ns ( 70.72 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top1" "UNKNOWN" "V1" "E:/课件/大三1/课程设计/top1/db/top1.quartus_db" { Floorplan "E:/课件/大三1/课程设计/top1/" "" "17.305 ns" { din2[2] NUM[2]~662 NUM[2]~670 SEG~1428 SEG~1433 LED_G } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "17.305 ns" { din2[2] din2[2]~out0 NUM[2]~662 NUM[2]~670 SEG~1428 SEG~1433 LED_G } { 0.000ns 0.000ns 6.323ns 1.522ns 1.399ns 0.415ns 2.579ns } { 0.000ns 1.475ns 0.442ns 0.292ns 0.292ns 0.442ns 2.124ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Jan 12 17:40:03 2008 " "Info: Processing ended: Sat Jan 12 17:40:03 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}