lpc23xx.h

周立功smartArm2300开发板中CAN总线示例程序。

#define CAN1SR 		(*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x1C))  	
#define CAN1RFS 	(*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x20))  	
#define CAN1RID 	(*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x24))
#define CAN1RDA 	(*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x28))  	
#define CAN1RDB 	(*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x2C))
  	
#define CAN1TFI1 	(*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x30))  	
#define CAN1TID1 	(*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x34))  	
#define CAN1TDA1 	(*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x38))
#define CAN1TDB1 	(*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x3C))  	
#define CAN1TFI2 	(*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x40))  	
#define CAN1TID2 	(*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x44))  	
#define CAN1TDA2 	(*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x48))  	
#define CAN1TDB2 	(*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x4C))
#define CAN1TFI3 	(*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x50))  	
#define CAN1TID3 	(*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x54))  	
#define CAN1TDA3 	(*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x58))  	
#define CAN1TDB3 	(*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x5C))

#define CAN2_BASE_ADDR		0xE0048000
#define CAN2MOD 	(*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x00))  	
#define CAN2CMR 	(*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x04))  	
#define CAN2GSR 	(*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x08))  	
#define CAN2ICR 	(*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x0C))  	
#define CAN2IER 	(*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x10))
#define CAN2BTR 	(*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x14))  	
#define CAN2EWL 	(*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x18))  	
#define CAN2SR 		(*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x1C))  	
#define CAN2RFS 	(*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x20))  	
#define CAN2RID 	(*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x24))
#define CAN2RDA 	(*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x28))  	
#define CAN2RDB 	(*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x2C))
  	
#define CAN2TFI1 	(*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x30))  	
#define CAN2TID1 	(*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x34))  	
#define CAN2TDA1 	(*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x38))
#define CAN2TDB1 	(*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x3C))  	
#define CAN2TFI2 	(*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x40))  	
#define CAN2TID2 	(*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x44))  	
#define CAN2TDA2 	(*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x48))  	
#define CAN2TDB2 	(*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x4C))
#define CAN2TFI3 	(*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x50))  	
#define CAN2TID3 	(*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x54))  	
#define CAN2TDA3 	(*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x58))  	
#define CAN2TDB3 	(*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x5C))


/* MultiMedia Card Interface(MCI) Controller */
#define MCI_BASE_ADDR		0xE008C000
#define MCIPower       (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x00))
#define MCIClock       (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x04))
#define MCIArgument    (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x08))
#define MCICommand     (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x0C))
#define MCIRespCmd     (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x10))
#define MCIResponse0   (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x14))
#define MCIResponse1   (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x18))
#define MCIResponse2   (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x1C))
#define MCIResponse3   (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x20))
#define MCIDataTimer   (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x24))
#define MCIDataLength  (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x28))
#define MCIDataCtrl    (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x2C))
#define MCIDataCnt     (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x30))
#define MCIStatus      (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x34))
#define MCIClear       (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x38))
#define MCIMask0       (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x3C))
#define MCIMask1       (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x40))
#define MCIFifoCnt     (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x48))
#define MCIFIFO        (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x80))


/* I2S Interface Controller (I2S) */
#define I2S_BASE_ADDR		0xE0088000
#define I2SDAO        (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x00))
#define I2SDAI        (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x04))
#define I2STXFIFO     (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x08))
#define I2SRXFIFO     (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x0C))
#define I2SSTATE      (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x10))
#define I2SDMA1       (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x14))
#define I2SDMA2       (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x18))
#define I2SIRQ        (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x1C))
#define I2STXRATE     (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x20))
#define I2SRXRATE     (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x24))


/* General-purpose DMA Controller */
#define DMA_BASE_ADDR		   0xFFE04000
#define DMACIntStatus          (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x000))
#define DMACIntTCStatus        (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x004))
#define DMACIntTCClear         (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x008))
#define DMACIntErrorStatus     (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x00C))
#define DMACIntErrClr          (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x010))
#define DMACRawIntTCStatus     (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x014))
#define DMACRawIntErrorStatus  (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x018))
#define DMACEnbldChns          (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x01C))
#define DMACSoftBReq           (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x020))
#define DMACSoftSReq           (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x024))
#define DMACSoftLBReq          (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x028))
#define DMACSoftLSReq          (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x02C))
#define DMACConfiguration      (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x030))
#define DMACSync               (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x034))

/* DMA channel 0 registers */
#define DMACC0SrcAddr          (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x100))
#define DMACC0DestAddr         (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x104))
#define DMACC0LLI              (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x108))
#define DMACC0Control          (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x10C))
#define DMACC0Configuration    (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x110))

/* DMA channel 1 registers */
#define DMACC1SrcAddr          (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x120))
#define DMACC1DestAddr         (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x124))
#define DMACC1LLI              (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x128))
#define DMACC1Control          (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x12C))
#define DMACC1Configuration    (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x130))


/* USB Controller */
#define USB_INT_BASE_ADDR	0xE01FC1C0
#define USB_BASE_ADDR		0xFFE0C200		/* USB Base Address */

#define  USBClkCtrl             	(*(volatile unsigned long *)(0xFFE0CFF4))  
#define  USBClkSt               	(*(volatile unsigned long *)(0xFFE0CFF8)) 
#define  USBPortSel             	(*(volatile unsigned long *)(0xFFE0C110))	/* LPC2378 Only */


#define USBIntSt			(*(volatile unsigned long *)(USB_INT_BASE_ADDR + 0x00))

/* USB Device Interrupt Registers */
#define USBDevIntSt			(*(volatile unsigned long *)(USB_BASE_ADDR + 0x00))
#define USBDevIntEn			(*(volatile unsigned long *)(USB_BASE_ADDR + 0x04))
#define USBDevIntClr		(*(volatile unsigned long *)(USB_BASE_ADDR + 0x08))
#define USBDevIntSet		(*(volatile unsigned long *)(USB_BASE_ADDR + 0x0C))
#define USBDevIntPri		(*(volatile unsigned long *)(USB_BASE_ADDR + 0x2C))

/* USB Device Endpoint Interrupt Registers */
#define USBEpIntSt			(*(volatile unsigned long *)(USB_BASE_ADDR + 0x30))
#define USBEpIntEn			(*(volatile unsigned long *)(USB_BASE_ADDR + 0x34))
#define USBEpIntClr			(*(volatile unsigned long *)(USB_BASE_ADDR + 0x38))
#define USBEpIntSet			(*(volatile unsigned long *)(USB_BASE_ADDR + 0x3C))
#define USBEpIntPri			(*(volatile unsigned long *)(USB_BASE_ADDR + 0x40))

/* USB Device Endpoint Realization Registers */
#define USBReEp				(*(volatile unsigned long *)(USB_BASE_ADDR + 0x44))
#define USBEpInd			(*(volatile unsigned long *)(USB_BASE_ADDR + 0x48))
#define USBMaxPSize			(*(volatile unsigned long *)(USB_BASE_ADDR + 0x4C))

/* USB Device Command Reagisters */
#define USBCmdCode			(*(volatile unsigned long *)(USB_BASE_ADDR + 0x10))
#define USBCmdData			(*(volatile unsigned long *)(USB_BASE_ADDR + 0x14))

/* USB Device Data Transfer Registers */
#define USBRxData			(*(volatile unsigned long *)(USB_BASE_ADDR + 0x18))
#define USBTxData			(*(volatile unsigned long *)(USB_BASE_ADDR + 0x1C))
#define USBRxPLen			(*(volatile unsigned long *)(USB_BASE_ADDR + 0x20))
#define USBTxPLen			(*(volatile unsigned long *)(USB_BASE_ADDR + 0x24))
#define USBCtrl				(*(volatile unsigned long *)(USB_BASE_ADDR + 0x28))

/* USB Device DMA Registers */
#define USBDMARSt           (*(volatile unsigned long *)(USB_BASE_ADDR + 0x50))
#define USBDMARClr          (*(volatile unsigned long *)(USB_BASE_ADDR + 0x54))
#define USBDMARSet          (*(volatile unsigned long *)(USB_BASE_ADDR + 0x58))
#define USBUDCAH            (*(volatile unsigned long *)(USB_BASE_ADDR + 0x80))
#define USBEpDMASt          (*(volatile unsigned long *)(USB_BASE_ADDR + 0x84))
#define USBEpDMAEn          (*(volatile unsigned long *)(USB_BASE_ADDR + 0x88))
#define USBEpDMADis         (*(volatile unsigned long *)(USB_BASE_ADDR + 0x8C))
#define USBDMAIntSt         (*(volatile unsigned long *)(USB_BASE_ADDR + 0x90))
#define USBDMAIntEn         (*(volatile unsigned long *)(USB_BASE_ADDR + 0x94))
#define USBEoTIntSt         (*(volatile unsigned long *)(USB_BASE_ADDR + 0xA0))
#define USBEoTIntClr        (*(volatile unsigned long *)(USB_BASE_ADDR + 0xA4))
#define USBEoTIntSet        (*(volatile unsigned long *)(USB_BASE_ADDR + 0xA8))
#define USBNDDRIntSt        (*(volatile unsigned long *)(USB_BASE_ADDR + 0xAC))
#define USBNDDRIntClr       (*(volatile unsigned long *)(USB_BASE_ADDR + 0xB0))
#define USBNDDRIntSet       (*(volatile unsigned long *)(USB_BASE_ADDR + 0xB4))
#define USBSysErrIntSt      (*(volatile unsigned long *)(USB_BASE_ADDR + 0xB8))
#define USBSysErrIntClr     (*(volatile unsigned long *)(USB_BASE_ADDR + 0xBC))
#define USBSysErrIntSet     (*(volatile unsigned long *)(USB_BASE_ADDR + 0xC0))

/* Ethernet MAC (32 bit data bus) -- all registers are RW unless indicated in parentheses */
#define MAC_BASE_ADDR		0xFFE00000 /* AHB Peripheral # 0 */
#define MAC_MAC1            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x000)) /* MAC config reg 1 */
#define MAC_MAC2            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x004)) /* MAC config reg 2 */
#define MAC_IPGT            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x008)) /* b2b InterPacketGap reg */
#define MAC_IPGR            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x00C)) /* non b2b InterPacketGap reg */
#define MAC_CLRT            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x010)) /* CoLlision window/ReTry reg */
#define MAC_MAXF            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x014)) /* MAXimum Frame reg */
#define MAC_SUPP            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x018)) /* PHY SUPPort reg */
#define MAC_TEST            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x01C)) /* TEST reg */
#define MAC_MCFG            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x020)) /* MII Mgmt ConFiG reg */
#define MAC_MCMD            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x024)) /* MII Mgmt CoMmanD reg */
#define MAC_MADR            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x028)) /* MII Mgmt ADdRess reg */
#define MAC_MWTD            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x02C)) /* MII Mgmt WriTe Data reg (WO) */
#define MAC_MRDD            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x030)) /* MII Mgmt ReaD Data reg (RO) */
#define MAC_MIND            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x034)) /* MII Mgmt INDicators reg (RO) */

#define MAC_SA0             (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x040)) /* Station Address 0 reg */
#define MAC_SA1             (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x044)) /* Station Address 1 reg */
#define MAC_SA2             (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x048)) /* Station Address 2 reg */

#define MAC_COMMAND         (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x100)) /* Command reg */
#define MAC_STATUS          (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x104)) /* Status reg (RO) */
#define MAC_RXDESCRIPTOR    (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x108)) /* Rx descriptor base address reg */
#define MAC_RXSTATUS        (*(volatile unsigned long *)(MAC_BASE