📄 timer.tan.qmsg

📁 该芯片的功能是： ① 有一复位开关
💻 QMSG
📖 第 1 页 / 共 3 页
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{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register counter4:u0\|dual_reg4:u3\|q\[0\] register counter4:u1\|dual_reg4:u3\|q\[3\] 338.87 MHz 2.951 ns Internal " "Info: Clock \"clk\" has Internal fmax of 338.87 MHz between source register \"counter4:u0\|dual_reg4:u3\|q\[0\]\" and destination register \"counter4:u1\|dual_reg4:u3\|q\[3\]\" (period= 2.951 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.785 ns + Longest register register " "Info: + Longest register to register delay is 2.785 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter4:u0\|dual_reg4:u3\|q\[0\] 1 REG LC_X21_Y29_N1 12 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X21_Y29_N1; Fanout = 12; REG Node = 'counter4:u0\|dual_reg4:u3\|q\[0\]'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { counter4:u0|dual_reg4:u3|q[0] } "NODE_NAME" } } { "dual_reg4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器模块/dual_reg4.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.552 ns) + CELL(0.366 ns) 0.918 ns counter4:u0\|zero_detect:u0\|Equal0~14 2 COMB LC_X22_Y29_N6 6 " "Info: 2: + IC(0.552 ns) + CELL(0.366 ns) = 0.918 ns; Loc. = LC_X22_Y29_N6; Fanout = 6; COMB Node = 'counter4:u0\|zero_detect:u0\|Equal0~14'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.918 ns" { counter4:u0|dual_reg4:u3|q[0] counter4:u0|zero_detect:u0|Equal0~14 } "NODE_NAME" } } { "zero_detect.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器模块/zero_detect.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.331 ns) + CELL(0.075 ns) 1.324 ns counter4:u1\|dual_reg4:u3\|q\[0\]~111 3 COMB LC_X22_Y29_N1 4 " "Info: 3: + IC(0.331 ns) + CELL(0.075 ns) = 1.324 ns; Loc. = LC_X22_Y29_N1; Fanout = 4; COMB Node = 'counter4:u1\|dual_reg4:u3\|q\[0\]~111'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.406 ns" { counter4:u0|zero_detect:u0|Equal0~14 counter4:u1|dual_reg4:u3|q[0]~111 } "NODE_NAME" } } { "dual_reg4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器模块/dual_reg4.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.756 ns) + CELL(0.705 ns) 2.785 ns counter4:u1\|dual_reg4:u3\|q\[3\] 4 REG LC_X22_Y29_N4 9 " "Info: 4: + IC(0.756 ns) + CELL(0.705 ns) = 2.785 ns; Loc. = LC_X22_Y29_N4; Fanout = 9; REG Node = 'counter4:u1\|dual_reg4:u3\|q\[3\]'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.461 ns" { counter4:u1|dual_reg4:u3|q[0]~111 counter4:u1|dual_reg4:u3|q[3] } "NODE_NAME" } } { "dual_reg4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器模块/dual_reg4.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.146 ns ( 41.15 % ) " "Info: Total cell delay = 1.146 ns ( 41.15 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.639 ns ( 58.85 % ) " "Info: Total interconnect delay = 1.639 ns ( 58.85 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.785 ns" { counter4:u0|dual_reg4:u3|q[0] counter4:u0|zero_detect:u0|Equal0~14 counter4:u1|dual_reg4:u3|q[0]~111 counter4:u1|dual_reg4:u3|q[3] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "2.785 ns" { counter4:u0|dual_reg4:u3|q[0] counter4:u0|zero_detect:u0|Equal0~14 counter4:u1|dual_reg4:u3|q[0]~111 counter4:u1|dual_reg4:u3|q[3] } { 0.000ns 0.552ns 0.331ns 0.756ns } { 0.000ns 0.366ns 0.075ns 0.705ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.922 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.922 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 16 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 16; CLK Node = 'clk'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "timer.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器模块/timer.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.552 ns) + CELL(0.542 ns) 2.922 ns counter4:u1\|dual_reg4:u3\|q\[3\] 2 REG LC_X22_Y29_N4 9 " "Info: 2: + IC(1.552 ns) + CELL(0.542 ns) = 2.922 ns; Loc. = LC_X22_Y29_N4; Fanout = 9; REG Node = 'counter4:u1\|dual_reg4:u3\|q\[3\]'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.094 ns" { clk counter4:u1|dual_reg4:u3|q[3] } "NODE_NAME" } } { "dual_reg4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器模块/dual_reg4.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 46.89 % ) " "Info: Total cell delay = 1.370 ns ( 46.89 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.552 ns ( 53.11 % ) " "Info: Total interconnect delay = 1.552 ns ( 53.11 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.922 ns" { clk counter4:u1|dual_reg4:u3|q[3] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "2.922 ns" { clk clk~out0 counter4:u1|dual_reg4:u3|q[3] } { 0.000ns 0.000ns 1.552ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.922 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.922 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 16 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 16; CLK Node = 'clk'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "timer.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器模块/timer.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.552 ns) + CELL(0.542 ns) 2.922 ns counter4:u0\|dual_reg4:u3\|q\[0\] 2 REG LC_X21_Y29_N1 12 " "Info: 2: + IC(1.552 ns) + CELL(0.542 ns) = 2.922 ns; Loc. = LC_X21_Y29_N1; Fanout = 12; REG Node = 'counter4:u0\|dual_reg4:u3\|q\[0\]'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.094 ns" { clk counter4:u0|dual_reg4:u3|q[0] } "NODE_NAME" } } { "dual_reg4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器模块/dual_reg4.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 46.89 % ) " "Info: Total cell delay = 1.370 ns ( 46.89 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.552 ns ( 53.11 % ) " "Info: Total interconnect delay = 1.552 ns ( 53.11 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.922 ns" { clk counter4:u0|dual_reg4:u3|q[0] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "2.922 ns" { clk clk~out0 counter4:u0|dual_reg4:u3|q[0] } { 0.000ns 0.000ns 1.552ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.922 ns" { clk counter4:u1|dual_reg4:u3|q[3] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "2.922 ns" { clk clk~out0 counter4:u1|dual_reg4:u3|q[3] } { 0.000ns 0.000ns 1.552ns } { 0.000ns 0.828ns 0.542ns } "" } } { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.922 ns" { clk counter4:u0|dual_reg4:u3|q[0] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "2.922 ns" { clk clk~out0 counter4:u0|dual_reg4:u3|q[0] } { 0.000ns 0.000ns 1.552ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "dual_reg4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器模块/dual_reg4.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "dual_reg4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器模块/dual_reg4.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.785 ns" { counter4:u0|dual_reg4:u3|q[0] counter4:u0|zero_detect:u0|Equal0~14 counter4:u1|dual_reg4:u3|q[0]~111 counter4:u1|dual_reg4:u3|q[3] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "2.785 ns" { counter4:u0|dual_reg4:u3|q[0] counter4:u0|zero_detect:u0|Equal0~14 counter4:u1|dual_reg4:u3|q[0]~111 counter4:u1|dual_reg4:u3|q[3] } { 0.000ns 0.552ns 0.331ns 0.756ns } { 0.000ns 0.366ns 0.075ns 0.705ns } "" } } { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.922 ns" { clk counter4:u1|dual_reg4:u3|q[3] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "2.922 ns" { clk clk~out0 counter4:u1|dual_reg4:u3|q[3] } { 0.000ns 0.000ns 1.552ns } { 0.000ns 0.828ns 0.542ns } "" } } { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.922 ns" { clk counter4:u0|dual_reg4:u3|q[0] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "2.922 ns" { clk clk~out0 counter4:u0|dual_reg4:u3|q[0] } { 0.000ns 0.000ns 1.552ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "counter4:u0\|dual_reg4:u3\|q\[3\] down clk 4.461 ns register " "Info: tsu for register \"counter4:u0\|dual_reg4:u3\|q\[3\]\" (data pin = \"down\", clock pin = \"clk\") is 4.461 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.373 ns + Longest pin register " "Info: + Longest pin to register delay is 7.373 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns down 1 PIN PIN_J16 1 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_J16; Fanout = 1; PIN Node = 'down'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { down } "NODE_NAME" } } { "timer.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器模块/timer.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.257 ns) + CELL(0.366 ns) 5.710 ns counter4:u0\|dual_reg4:u3\|q\[0\]~86 2 COMB LC_X22_Y30_N2 4 " "Info: 2: + IC(4.257 ns) + CELL(0.366 ns) = 5.710 ns; Loc. = LC_X22_Y30_N2; Fanout = 4; COMB Node = 'counter4:u0\|dual_reg4:u3\|q\[0\]~86'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.623 ns" { down counter4:u0|dual_reg4:u3|q[0]~86 } "NODE_NAME" } } { "dual_reg4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器模块/dual_reg4.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.958 ns) + CELL(0.705 ns) 7.373 ns counter4:u0\|dual_reg4:u3\|q\[3\] 3 REG LC_X21_Y29_N2 9 " "Info: 3: + IC(0.958 ns) + CELL(0.705 ns) = 7.373 ns; Loc. = LC_X21_Y29_N2; Fanout = 9; REG Node = 'counter4:u0\|dual_reg4:u3\|q\[3\]'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.663 ns" { counter4:u0|dual_reg4:u3|q[0]~86 counter4:u0|dual_reg4:u3|q[3] } "NODE_NAME" } } { "dual_reg4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器模块/dual_reg4.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.158 ns ( 29.27 % ) " "Info: Total cell delay = 2.158 ns ( 29.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.215 ns ( 70.73 % ) " "Info: Total interconnect delay = 5.215 ns ( 70.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.373 ns" { down counter4:u0|dual_reg4:u3|q[0]~86 counter4:u0|dual_reg4:u3|q[3] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "7.373 ns" { down down~out0 counter4:u0|dual_reg4:u3|q[0]~86 counter4:u0|dual_reg4:u3|q[3] } { 0.000ns 0.000ns 4.257ns 0.958ns } { 0.000ns 1.087ns 0.366ns 0.705ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "dual_reg4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器模块/dual_reg4.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.922 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.922 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 16 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 16; CLK Node = 'clk'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "timer.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器模块/timer.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.552 ns) + CELL(0.542 ns) 2.922 ns counter4:u0\|dual_reg4:u3\|q\[3\] 2 REG LC_X21_Y29_N2 9 " "Info: 2: + IC(1.552 ns) + CELL(0.542 ns) = 2.922 ns; Loc. = LC_X21_Y29_N2; Fanout = 9; REG Node = 'counter4:u0\|dual_reg4:u3\|q\[3\]'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.094 ns" { clk counter4:u0|dual_reg4:u3|q[3] } "NODE_NAME" } } { "dual_reg4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器模块/dual_reg4.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 46.89 % ) " "Info: Total cell delay = 1.370 ns ( 46.89 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.552 ns ( 53.11 % ) " "Info: Total interconnect delay = 1.552 ns ( 53.11 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.922 ns" { clk counter4:u0|dual_reg4:u3|q[3] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "2.922 ns" { clk clk~out0 counter4:u0|dual_reg4:u3|q[3] } { 0.000ns 0.000ns 1.552ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.373 ns" { down counter4:u0|dual_reg4:u3|q[0]~86 counter4:u0|dual_reg4:u3|q[3] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "7.373 ns" { down down~out0 counter4:u0|dual_reg4:u3|q[0]~86 counter4:u0|dual_reg4:u3|q[3] } { 0.000ns 0.000ns 4.257ns 0.958ns } { 0.000ns 1.087ns 0.366ns 0.705ns } "" } } { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.922 ns" { clk counter4:u0|dual_reg4:u3|q[3] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "2.922 ns" { clk clk~out0 counter4:u0|dual_reg4:u3|q[3] } { 0.000ns 0.000ns 1.552ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk done counter4:u1\|dual_reg4:u3\|q\[3\] 8.897 ns register " "Info: tco from clock \"clk\" to destination pin \"done\" through register \"counter4:u1\|dual_reg4:u3\|q\[3\]\" is 8.897 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.922 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.922 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 16 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 16; CLK Node = 'clk'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "timer.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器模块/timer.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.552 ns) + CELL(0.542 ns) 2.922 ns counter4:u1\|dual_reg4:u3\|q\[3\] 2 REG LC_X22_Y29_N4 9 " "Info: 2: + IC(1.552 ns) + CELL(0.542 ns) = 2.922 ns; Loc. = LC_X22_Y29_N4; Fanout = 9; REG Node = 'counter4:u1\|dual_reg4:u3\|q\[3\]'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.094 ns" { clk counter4:u1|dual_reg4:u3|q[3] } "NODE_NAME" } } { "dual_reg4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器模块/dual_reg4.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 46.89 % ) " "Info: Total cell delay = 1.370 ns ( 46.89 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.552 ns ( 53.11 % ) " "Info: Total interconnect delay = 1.552 ns ( 53.11 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.922 ns" { clk counter4:u1|dual_reg4:u3|q[3] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "2.922 ns" { clk clk~out0 counter4:u1|dual_reg4:u3|q[3] } { 0.000ns 0.000ns 1.552ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "dual_reg4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器模块/dual_reg4.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.819 ns + Longest register pin " "Info: + Longest register to pin delay is 5.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter4:u1\|dual_reg4:u3\|q\[3\] 1 REG LC_X22_Y29_N4 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X22_Y29_N4; Fanout = 9; REG Node = 'counter4:u1\|dual_reg4:u3\|q\[3\]'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { counter4:u1|dual_reg4:u3|q[3] } "NODE_NAME" } } { "dual_reg4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器模块/dual_reg4.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.394 ns) + CELL(0.366 ns) 0.760 ns counter4:u1\|zero_detect:u0\|Equal0~14 2 COMB LC_X22_Y29_N7 6 " "Info: 2: + IC(0.394 ns) + CELL(0.366 ns) = 0.760 ns; Loc. = LC_X22_Y29_N7; Fanout = 6; COMB Node = 'counter4:u1\|zero_detect:u0\|Equal0~14'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.760 ns" { counter4:u1|dual_reg4:u3|q[3] counter4:u1|zero_detect:u0|Equal0~14 } "NODE_NAME" } } { "zero_detect.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器模块/zero_detect.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.995 ns) + CELL(0.280 ns) 2.035 ns done~44 3 COMB LC_X29_Y29_N4 1 " "Info: 3: + IC(0.995 ns) + CELL(0.280 ns) = 2.035 ns; Loc. = LC_X29_Y29_N4; Fanout = 1; COMB Node = 'done~44'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.275 ns" { counter4:u1|zero_detect:u0|Equal0~14 done~44 } "NODE_NAME" } } { "timer.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器模块/timer.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.380 ns) + CELL(2.404 ns) 5.819 ns done 4 PIN PIN_E9 0 " "Info: 4: + IC(1.380 ns) + CELL(2.404 ns) = 5.819 ns; Loc. = PIN_E9; Fanout = 0; PIN Node = 'done'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.784 ns" { done~44 done } "NODE_NAME" } } { "timer.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器模块/timer.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.050 ns ( 52.41 % ) " "Info: Total cell delay = 3.050 ns ( 52.41 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.769 ns ( 47.59 % ) " "Info: Total interconnect delay = 2.769 ns ( 47.59 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.819 ns" { counter4:u1|dual_reg4:u3|q[3] counter4:u1|zero_detect:u0|Equal0~14 done~44 done } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "5.819 ns" { counter4:u1|dual_reg4:u3|q[3] counter4:u1|zero_detect:u0|Equal0~14 done~44 done } { 0.000ns 0.394ns 0.995ns 1.380ns } { 0.000ns 0.366ns 0.280ns 2.404ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.922 ns" { clk counter4:u1|dual_reg4:u3|q[3] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "2.922 ns" { clk clk~out0 counter4:u1|dual_reg4:u3|q[3] } { 0.000ns 0.000ns 1.552ns } { 0.000ns 0.828ns 0.542ns } "" } } { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.819 ns" { counter4:u1|dual_reg4:u3|q[3] counter4:u1|zero_detect:u0|Equal0~14 done~44 done } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "5.819 ns" { counter4:u1|dual_reg4:u3|q[3] counter4:u1|zero_detect:u0|Equal0~14 done~44 done } { 0.000ns 0.394ns 0.995ns 1.380ns } { 0.000ns 0.366ns 0.280ns 2.404ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "counter4:u0\|dual_reg4:u3\|q\[1\] data\[1\] clk -1.737 ns register " "Info: th for register \"counter4:u0\|dual_reg4:u3\|q\[1\]\" (data pin = \"data\[1\]\", clock pin = \"clk\") is -1.737 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.922 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.922 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 16 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 16; CLK Node = 'clk'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "timer.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器模块/timer.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.552 ns) + CELL(0.542 ns) 2.922 ns counter4:u0\|dual_reg4:u3\|q\[1\] 2 REG LC_X21_Y29_N4 11 " "Info: 2: + IC(1.552 ns) + CELL(0.542 ns) = 2.922 ns; Loc. = LC_X21_Y29_N4; Fanout = 11; REG Node = 'counter4:u0\|dual_reg4:u3\|q\[1\]'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.094 ns" { clk counter4:u0|dual_reg4:u3|q[1] } "NODE_NAME" } } { "dual_reg4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器模块/dual_reg4.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 46.89 % ) " "Info: Total cell delay = 1.370 ns ( 46.89 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.552 ns ( 53.11 % ) " "Info: Total interconnect delay = 1.552 ns ( 53.11 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.922 ns" { clk counter4:u0|dual_reg4:u3|q[1] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "2.922 ns" { clk clk~out0 counter4:u0|dual_reg4:u3|q[1] } { 0.000ns 0.000ns 1.552ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" {  } { { "dual_reg4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器模块/dual_reg4.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.759 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.759 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.972 ns) 0.972 ns data\[1\] 1 PIN PIN_B14 1 " "Info: 1: + IC(0.000 ns) + CELL(0.972 ns) = 0.972 ns; Loc. = PIN_B14; Fanout = 1; PIN Node = 'data\[1\]'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { data[1] } "NODE_NAME" } } { "timer.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器模块/timer.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.702 ns) + CELL(0.085 ns) 4.759 ns counter4:u0\|dual_reg4:u3\|q\[1\] 2 REG LC_X21_Y29_N4 11 " "Info: 2: + IC(3.702 ns) + CELL(0.085 ns) = 4.759 ns; Loc. = LC_X21_Y29_N4; Fanout = 11; REG Node = 'counter4:u0\|dual_reg4:u3\|q\[1\]'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.787 ns" { data[1] counter4:u0|dual_reg4:u3|q[1] } "NODE_NAME" } } { "dual_reg4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器模块/dual_reg4.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.057 ns ( 22.21 % ) " "Info: Total cell delay = 1.057 ns ( 22.21 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.702 ns ( 77.79 % ) " "Info: Total interconnect delay = 3.702 ns ( 77.79 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.759 ns" { data[1] counter4:u0|dual_reg4:u3|q[1] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "4.759 ns" { data[1] data[1]~out0 counter4:u0|dual_reg4:u3|q[1] } { 0.000ns 0.000ns 3.702ns } { 0.000ns 0.972ns 0.085ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.922 ns" { clk counter4:u0|dual_reg4:u3|q[1] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "2.922 ns" { clk clk~out0 counter4:u0|dual_reg4:u3|q[1] } { 0.000ns 0.000ns 1.552ns } { 0.000ns 0.828ns 0.542ns } "" } } { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.759 ns" { data[1] counter4:u0|dual_reg4:u3|q[1] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "4.759 ns" { data[1] data[1]~out0 counter4:u0|dual_reg4:u3|q[1] } { 0.000ns 0.000ns 3.702ns } { 0.000ns 0.972ns 0.085ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
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