timer.fit.qmsg

该芯片的功能是： ① 有一复位开关

{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" {  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "47 unused 3.30 18 29 0 " "Info: Number of I/O pins in group: 47 (unused VREF, 3.30 VCCIO, 18 input, 29 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "Info: I/O standards used: 3.3-V LVTTL." {  } {  } 0 0 "I/O standards used: %1!s!" 0 0}  } {  } 0 0 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0}  } {  } 0 0 "Statistics of %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use unused 1 28 " "Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  28 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 0 30 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  30 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use unused 0 51 " "Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  51 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use unused 1 51 " "Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  51 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use unused 0 29 " "Info: I/O bank number 5 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  29 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use unused 0 29 " "Info: I/O bank number 6 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  29 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use unused 0 52 " "Info: I/O bank number 7 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  52 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use unused 0 51 " "Info: I/O bank number 8 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  51 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "9 does not use unused 0 6 " "Info: I/O bank number 9 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  6 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "10 does not use unused 0 0 " "Info: I/O bank number 10 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  0 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "11 does not use unused 0 6 " "Info: I/O bank number 11 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  6 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "12 does not use unused 0 0 " "Info: I/O bank number 12 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  0 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0}  } {  } 0 0 "Statistics of %1!s!" 0 0}  } {  } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "2.508 ns register register " "Info: Estimated most critical path is register to register delay of 2.508 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter4:u1\|dual_reg4:u3\|q\[1\] 1 REG LAB_X22_Y29 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X22_Y29; Fanout = 11; REG Node = 'counter4:u1\|dual_reg4:u3\|q\[1\]'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { counter4:u1|dual_reg4:u3|q[1] } "NODE_NAME" } } { "dual_reg4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器模块/dual_reg4.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.451 ns) + CELL(0.075 ns) 0.526 ns counter4:u1\|zero_detect:u0\|Equal0~14 2 COMB LAB_X22_Y29 6 " "Info: 2: + IC(0.451 ns) + CELL(0.075 ns) = 0.526 ns; Loc. = LAB_X22_Y29; Fanout = 6; COMB Node = 'counter4:u1\|zero_detect:u0\|Equal0~14'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.526 ns" { counter4:u1|dual_reg4:u3|q[1] counter4:u1|zero_detect:u0|Equal0~14 } "NODE_NAME" } } { "zero_detect.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器模块/zero_detect.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.102 ns) + CELL(0.366 ns) 0.994 ns counter4:u2\|dual_reg4:u3\|q\[0\]~111 3 COMB LAB_X22_Y29 4 " "Info: 3: + IC(0.102 ns) + CELL(0.366 ns) = 0.994 ns; Loc. = LAB_X22_Y29; Fanout = 4; COMB Node = 'counter4:u2\|dual_reg4:u3\|q\[0\]~111'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.468 ns" { counter4:u1|zero_detect:u0|Equal0~14 counter4:u2|dual_reg4:u3|q[0]~111 } "NODE_NAME" } } { "dual_reg4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器模块/dual_reg4.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.809 ns) + CELL(0.705 ns) 2.508 ns counter4:u2\|dual_reg4:u3\|q\[3\] 4 REG LAB_X30_Y29 9 " "Info: 4: + IC(0.809 ns) + CELL(0.705 ns) = 2.508 ns; Loc. = LAB_X30_Y29; Fanout = 9; REG Node = 'counter4:u2\|dual_reg4:u3\|q\[3\]'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.514 ns" { counter4:u2|dual_reg4:u3|q[0]~111 counter4:u2|dual_reg4:u3|q[3] } "NODE_NAME" } } { "dual_reg4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器模块/dual_reg4.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.146 ns ( 45.69 % ) " "Info: Total cell delay = 1.146 ns ( 45.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.362 ns ( 54.31 % ) " "Info: Total interconnect delay = 1.362 ns ( 54.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.508 ns" { counter4:u1|dual_reg4:u3|q[1] counter4:u1|zero_detect:u0|Equal0~14 counter4:u2|dual_reg4:u3|q[0]~111 counter4:u2|dual_reg4:u3|q[3] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 0 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "X21_Y21 X31_Y31 " "Info: The peak interconnect region extends from location X21_Y21 to location X31_Y31" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}