timer.tan.rpt

该芯片的功能是： ① 有一复位开关

; N/A           ; None        ; -2.823 ns ; load     ; counter4:u0|dual_reg4:u3|q[0] ; clk      ;
; N/A           ; None        ; -2.823 ns ; load     ; counter4:u0|dual_reg4:u3|q[2] ; clk      ;
; N/A           ; None        ; -2.823 ns ; load     ; counter4:u0|dual_reg4:u3|q[1] ; clk      ;
; N/A           ; None        ; -2.842 ns ; load     ; counter4:u1|dual_reg4:u3|q[3] ; clk      ;
; N/A           ; None        ; -2.842 ns ; load     ; counter4:u1|dual_reg4:u3|q[2] ; clk      ;
; N/A           ; None        ; -2.842 ns ; load     ; counter4:u1|dual_reg4:u3|q[0] ; clk      ;
; N/A           ; None        ; -2.842 ns ; load     ; counter4:u1|dual_reg4:u3|q[1] ; clk      ;
; N/A           ; None        ; -3.011 ns ; load     ; counter4:u2|dual_reg4:u3|q[3] ; clk      ;
; N/A           ; None        ; -3.011 ns ; load     ; counter4:u2|dual_reg4:u3|q[2] ; clk      ;
; N/A           ; None        ; -3.011 ns ; load     ; counter4:u2|dual_reg4:u3|q[0] ; clk      ;
; N/A           ; None        ; -3.011 ns ; load     ; counter4:u2|dual_reg4:u3|q[1] ; clk      ;
; N/A           ; None        ; -3.024 ns ; load     ; counter4:u3|dual_reg4:u3|q[3] ; clk      ;
; N/A           ; None        ; -3.024 ns ; load     ; counter4:u3|dual_reg4:u3|q[2] ; clk      ;
; N/A           ; None        ; -3.024 ns ; load     ; counter4:u3|dual_reg4:u3|q[0] ; clk      ;
; N/A           ; None        ; -3.024 ns ; load     ; counter4:u3|dual_reg4:u3|q[1] ; clk      ;
; N/A           ; None        ; -4.351 ns ; down     ; counter4:u0|dual_reg4:u3|q[3] ; clk      ;
; N/A           ; None        ; -4.351 ns ; down     ; counter4:u0|dual_reg4:u3|q[0] ; clk      ;
; N/A           ; None        ; -4.351 ns ; down     ; counter4:u0|dual_reg4:u3|q[2] ; clk      ;
; N/A           ; None        ; -4.351 ns ; down     ; counter4:u0|dual_reg4:u3|q[1] ; clk      ;
+---------------+-------------+-----------+----------+-------------------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Thu Sep 27 15:51:01 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off timer -c timer --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 338.87 MHz between source register "counter4:u0|dual_reg4:u3|q[0]" and destination register "counter4:u1|dual_reg4:u3|q[3]" (period= 2.951 ns)
    Info: + Longest register to register delay is 2.785 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X21_Y29_N1; Fanout = 12; REG Node = 'counter4:u0|dual_reg4:u3|q[0]'
        Info: 2: + IC(0.552 ns) + CELL(0.366 ns) = 0.918 ns; Loc. = LC_X22_Y29_N6; Fanout = 6; COMB Node = 'counter4:u0|zero_detect:u0|Equal0~14'
        Info: 3: + IC(0.331 ns) + CELL(0.075 ns) = 1.324 ns; Loc. = LC_X22_Y29_N1; Fanout = 4; COMB Node = 'counter4:u1|dual_reg4:u3|q[0]~111'
        Info: 4: + IC(0.756 ns) + CELL(0.705 ns) = 2.785 ns; Loc. = LC_X22_Y29_N4; Fanout = 9; REG Node = 'counter4:u1|dual_reg4:u3|q[3]'
        Info: Total cell delay = 1.146 ns ( 41.15 % )
        Info: Total interconnect delay = 1.639 ns ( 58.85 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.922 ns
            Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 16; CLK Node = 'clk'
            Info: 2: + IC(1.552 ns) + CELL(0.542 ns) = 2.922 ns; Loc. = LC_X22_Y29_N4; Fanout = 9; REG Node = 'counter4:u1|dual_reg4:u3|q[3]'
            Info: Total cell delay = 1.370 ns ( 46.89 % )
            Info: Total interconnect delay = 1.552 ns ( 53.11 % )
        Info: - Longest clock path from clock "clk" to source register is 2.922 ns
            Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 16; CLK Node = 'clk'
            Info: 2: + IC(1.552 ns) + CELL(0.542 ns) = 2.922 ns; Loc. = LC_X21_Y29_N1; Fanout = 12; REG Node = 'counter4:u0|dual_reg4:u3|q[0]'
            Info: Total cell delay = 1.370 ns ( 46.89 % )
            Info: Total interconnect delay = 1.552 ns ( 53.11 % )
    Info: + Micro clock to output delay of source is 0.156 ns
    Info: + Micro setup delay of destination is 0.010 ns
Info: tsu for register "counter4:u0|dual_reg4:u3|q[3]" (data pin = "down", clock pin = "clk") is 4.461 ns
    Info: + Longest pin to register delay is 7.373 ns
        Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_J16; Fanout = 1; PIN Node = 'down'
        Info: 2: + IC(4.257 ns) + CELL(0.366 ns) = 5.710 ns; Loc. = LC_X22_Y30_N2; Fanout = 4; COMB Node = 'counter4:u0|dual_reg4:u3|q[0]~86'
        Info: 3: + IC(0.958 ns) + CELL(0.705 ns) = 7.373 ns; Loc. = LC_X21_Y29_N2; Fanout = 9; REG Node = 'counter4:u0|dual_reg4:u3|q[3]'
        Info: Total cell delay = 2.158 ns ( 29.27 % )
        Info: Total interconnect delay = 5.215 ns ( 70.73 % )
    Info: + Micro setup delay of destination is 0.010 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.922 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 16; CLK Node = 'clk'
        Info: 2: + IC(1.552 ns) + CELL(0.542 ns) = 2.922 ns; Loc. = LC_X21_Y29_N2; Fanout = 9; REG Node = 'counter4:u0|dual_reg4:u3|q[3]'
        Info: Total cell delay = 1.370 ns ( 46.89 % )
        Info: Total interconnect delay = 1.552 ns ( 53.11 % )
Info: tco from clock "clk" to destination pin "done" through register "counter4:u1|dual_reg4:u3|q[3]" is 8.897 ns
    Info: + Longest clock path from clock "clk" to source register is 2.922 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 16; CLK Node = 'clk'
        Info: 2: + IC(1.552 ns) + CELL(0.542 ns) = 2.922 ns; Loc. = LC_X22_Y29_N4; Fanout = 9; REG Node = 'counter4:u1|dual_reg4:u3|q[3]'
        Info: Total cell delay = 1.370 ns ( 46.89 % )
        Info: Total interconnect delay = 1.552 ns ( 53.11 % )
    Info: + Micro clock to output delay of source is 0.156 ns
    Info: + Longest register to pin delay is 5.819 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X22_Y29_N4; Fanout = 9; REG Node = 'counter4:u1|dual_reg4:u3|q[3]'
        Info: 2: + IC(0.394 ns) + CELL(0.366 ns) = 0.760 ns; Loc. = LC_X22_Y29_N7; Fanout = 6; COMB Node = 'counter4:u1|zero_detect:u0|Equal0~14'
        Info: 3: + IC(0.995 ns) + CELL(0.280 ns) = 2.035 ns; Loc. = LC_X29_Y29_N4; Fanout = 1; COMB Node = 'done~44'
        Info: 4: + IC(1.380 ns) + CELL(2.404 ns) = 5.819 ns; Loc. = PIN_E9; Fanout = 0; PIN Node = 'done'
        Info: Total cell delay = 3.050 ns ( 52.41 % )
        Info: Total interconnect delay = 2.769 ns ( 47.59 % )
Info: th for register "counter4:u0|dual_reg4:u3|q[1]" (data pin = "data[1]", clock pin = "clk") is -1.737 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.922 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 16; CLK Node = 'clk'
        Info: 2: + IC(1.552 ns) + CELL(0.542 ns) = 2.922 ns; Loc. = LC_X21_Y29_N4; Fanout = 11; REG Node = 'counter4:u0|dual_reg4:u3|q[1]'
        Info: Total cell delay = 1.370 ns ( 46.89 % )
        Info: Total interconnect delay = 1.552 ns ( 53.11 % )
    Info: + Micro hold delay of destination is 0.100 ns
    Info: - Shortest pin to register delay is 4.759 ns
        Info: 1: + IC(0.000 ns) + CELL(0.972 ns) = 0.972 ns; Loc. = PIN_B14; Fanout = 1; PIN Node = 'data[1]'
        Info: 2: + IC(3.702 ns) + CELL(0.085 ns) = 4.759 ns; Loc. = LC_X21_Y29_N4; Fanout = 11; REG Node = 'counter4:u0|dual_reg4:u3|q[1]'
        Info: Total cell delay = 1.057 ns ( 22.21 % )
        Info: Total interconnect delay = 3.702 ns ( 77.79 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 101 megabytes of memory during processing
    Info: Processing ended: Thu Sep 27 15:51:02 2007
    Info: Elapsed time: 00:00:01