timer.sim.rpt

该芯片的功能是： ① 有一复位开关

; |timer|counter4:u0|dual_reg4:u3|q[0]                                                            ; |timer|counter4:u0|dual_reg4:u3|q[0]                                                            ; regout           ;
; |timer|counter4:u0|dual_reg4:u3|q[1]                                                            ; |timer|counter4:u0|dual_reg4:u3|q[1]                                                            ; regout           ;
; |timer|counter4:u0|dual_reg4:u3|q[2]                                                            ; |timer|counter4:u0|dual_reg4:u3|q[2]                                                            ; regout           ;
; |timer|counter4:u0|dual_reg4:u3|q[3]                                                            ; |timer|counter4:u0|dual_reg4:u3|q[3]                                                            ; regout           ;
; |timer|counter4:u0|decr4:u2|dec_out[3]                                                          ; |timer|counter4:u0|decr4:u2|dec_out[3]                                                          ; out              ;
; |timer|counter4:u0|decr4:u2|dec_out[2]                                                          ; |timer|counter4:u0|decr4:u2|dec_out[2]                                                          ; out              ;
; |timer|counter4:u0|decr4:u2|dec_out[1]                                                          ; |timer|counter4:u0|decr4:u2|dec_out[1]                                                          ; out              ;
; |timer|counter4:u0|decr4:u2|dec_out[0]                                                          ; |timer|counter4:u0|decr4:u2|dec_out[0]                                                          ; out              ;
; |timer|counter4:u1|dual_reg4:u3|q~0                                                             ; |timer|counter4:u1|dual_reg4:u3|q~0                                                             ; out              ;
; |timer|counter4:u1|dual_reg4:u3|q~1                                                             ; |timer|counter4:u1|dual_reg4:u3|q~1                                                             ; out              ;
; |timer|counter4:u1|dual_reg4:u3|q~2                                                             ; |timer|counter4:u1|dual_reg4:u3|q~2                                                             ; out              ;
; |timer|counter4:u1|dual_reg4:u3|q~3                                                             ; |timer|counter4:u1|dual_reg4:u3|q~3                                                             ; out              ;
; |timer|counter4:u1|dual_reg4:u3|q~5                                                             ; |timer|counter4:u1|dual_reg4:u3|q~5                                                             ; out              ;
; |timer|counter4:u1|dual_reg4:u3|q~6                                                             ; |timer|counter4:u1|dual_reg4:u3|q~6                                                             ; out              ;
; |timer|counter4:u1|dual_reg4:u3|q~7                                                             ; |timer|counter4:u1|dual_reg4:u3|q~7                                                             ; out              ;
; |timer|counter4:u1|dual_reg4:u3|q[0]                                                            ; |timer|counter4:u1|dual_reg4:u3|q[0]                                                            ; regout           ;
; |timer|counter4:u1|dual_reg4:u3|q[1]                                                            ; |timer|counter4:u1|dual_reg4:u3|q[1]                                                            ; regout           ;
; |timer|counter4:u1|dual_reg4:u3|q[2]                                                            ; |timer|counter4:u1|dual_reg4:u3|q[2]                                                            ; regout           ;
; |timer|counter4:u1|dual_reg4:u3|q[3]                                                            ; |timer|counter4:u1|dual_reg4:u3|q[3]                                                            ; regout           ;
; |timer|counter4:u1|decr4:u2|dec_out[3]                                                          ; |timer|counter4:u1|decr4:u2|dec_out[3]                                                          ; out              ;
; |timer|counter4:u1|decr4:u2|dec_out[2]                                                          ; |timer|counter4:u1|decr4:u2|dec_out[2]                                                          ; out              ;
; |timer|counter4:u1|decr4:u2|dec_out[1]                                                          ; |timer|counter4:u1|decr4:u2|dec_out[1]                                                          ; out              ;
; |timer|counter4:u1|decr4:u2|dec_out[0]                                                          ; |timer|counter4:u1|decr4:u2|dec_out[0]                                                          ; out              ;
; |timer|counter4:u2|dual_reg4:u3|q~0                                                             ; |timer|counter4:u2|dual_reg4:u3|q~0                                                             ; out              ;
; |timer|counter4:u2|dual_reg4:u3|q~1                                                             ; |timer|counter4:u2|dual_reg4:u3|q~1                                                             ; out              ;
; |timer|counter4:u2|dual_reg4:u3|q~2                                                             ; |timer|counter4:u2|dual_reg4:u3|q~2                                                             ; out              ;
; |timer|counter4:u2|dual_reg4:u3|q~3                                                             ; |timer|counter4:u2|dual_reg4:u3|q~3                                                             ; out              ;
; |timer|counter4:u2|dual_reg4:u3|q~4                                                             ; |timer|counter4:u2|dual_reg4:u3|q~4                                                             ; out              ;
; |timer|counter4:u2|dual_reg4:u3|q~5                                                             ; |timer|counter4:u2|dual_reg4:u3|q~5                                                             ; out              ;
; |timer|counter4:u2|dual_reg4:u3|q~6                                                             ; |timer|counter4:u2|dual_reg4:u3|q~6                                                             ; out              ;
; |timer|counter4:u2|dual_reg4:u3|q~7                                                             ; |timer|counter4:u2|dual_reg4:u3|q~7                                                             ; out              ;
; |timer|counter4:u2|dual_reg4:u3|q[0]                                                            ; |timer|counter4:u2|dual_reg4:u3|q[0]                                                            ; regout           ;
; |timer|counter4:u2|dual_reg4:u3|q[1]                                                            ; |timer|counter4:u2|dual_reg4:u3|q[1]                                                            ; regout           ;
; |timer|counter4:u2|dual_reg4:u3|q[2]                                                            ; |timer|counter4:u2|dual_reg4:u3|q[2]                                                            ; regout           ;
; |timer|counter4:u2|dual_reg4:u3|q[3]                                                            ; |timer|counter4:u2|dual_reg4:u3|q[3]                                                            ; regout           ;
; |timer|counter4:u2|decr4:u2|dec_out[3]                                                          ; |timer|counter4:u2|decr4:u2|dec_out[3]                                                          ; out              ;
; |timer|counter4:u2|decr4:u2|dec_out[2]                                                          ; |timer|counter4:u2|decr4:u2|dec_out[2]                                                          ; out              ;
; |timer|counter4:u2|decr4:u2|dec_out[1]                                                          ; |timer|counter4:u2|decr4:u2|dec_out[1]                                                          ; out              ;
; |timer|counter4:u2|decr4:u2|dec_out[0]                                                          ; |timer|counter4:u2|decr4:u2|dec_out[0]                                                          ; out              ;
; |timer|counter4:u3|dual_reg4:u3|q~0                                                             ; |timer|counter4:u3|dual_reg4:u3|q~0                                                             ; out              ;
; |timer|counter4:u3|dual_reg4:u3|q~1                                                             ; |timer|counter4:u3|dual_reg4:u3|q~1                                                             ; out              ;
; |timer|counter4:u3|dual_reg4:u3|q~2                                                             ; |timer|counter4:u3|dual_reg4:u3|q~2                                                             ; out              ;
; |timer|counter4:u3|dual_reg4:u3|q~3                                                             ; |timer|counter4:u3|dual_reg4:u3|q~3                                                             ; out              ;
; |timer|counter4:u3|dual_reg4:u3|q~5                                                             ; |timer|counter4:u3|dual_reg4:u3|q~5                                                             ; out              ;
; |timer|counter4:u3|dual_reg4:u3|q~6                                                             ; |timer|counter4:u3|dual_reg4:u3|q~6                                                             ; out              ;
; |timer|counter4:u3|dual_reg4:u3|q~7                                                             ; |timer|counter4:u3|dual_reg4:u3|q~7                                                             ; out              ;
; |timer|counter4:u3|dual_reg4:u3|q[0]                                                            ; |timer|counter4:u3|dual_reg4:u3|q[0]                                                            ; regout           ;
; |timer|counter4:u3|dual_reg4:u3|q[1]                                                            ; |timer|counter4:u3|dual_reg4:u3|q[1]                                                            ; regout           ;
; |timer|counter4:u3|dual_reg4:u3|q[2]                                                            ; |timer|counter4:u3|dual_reg4:u3|q[2]                                                            ; regout           ;
; |timer|counter4:u3|dual_reg4:u3|q[3]                                                            ; |timer|counter4:u3|dual_reg4:u3|q[3]                                                            ; regout           ;
; |timer|counter4:u3|decr4:u2|dec_out[3]                                                          ; |timer|counter4:u3|decr4:u2|dec_out[3]                                                          ; out              ;
; |timer|counter4:u3|decr4:u2|dec_out[2]                                                          ; |timer|counter4:u3|decr4:u2|dec_out[2]                                                          ; out              ;
; |timer|counter4:u3|decr4:u2|dec_out[1]                                                          ; |timer|counter4:u3|decr4:u2|dec_out[1]                                                          ; out              ;
; |timer|counter4:u3|decr4:u2|dec_out[0]                                                          ; |timer|counter4:u3|decr4:u2|dec_out[0]                                                          ; out              ;
; |timer|counter4:u0|decr4:u2|Equal0~6                                                            ; |timer|counter4:u0|decr4:u2|Equal0~6                                                            ; out0             ;
; |timer|counter4:u0|zero_detect:u0|Equal0~5                                                      ; |timer|counter4:u0|zero_detect:u0|Equal0~5                                                      ; out0             ;
; |timer|counter4:u1|decr4:u2|Equal0~6                                                            ; |timer|counter4:u1|decr4:u2|Equal0~6                                                            ; out0             ;
; |timer|counter4:u1|zero_detect:u0|Equal0~5                                                      ; |timer|counter4:u1|zero_detect:u0|Equal0~5                                                      ; out0             ;
; |timer|counter4:u2|decr4:u2|Equal0~6                                                            ; |timer|counter4:u2|decr4:u2|Equal0~6                                                            ; out0             ;
; |timer|counter4:u2|zero_detect:u0|Equal0~5                                                      ; |timer|counter4:u2|zero_detect:u0|Equal0~5                                                      ; out0             ;
; |timer|counter4:u3|decr4:u2|Equal0~6                                                            ; |timer|counter4:u3|decr4:u2|Equal0~6                                                            ; out0             ;
; |timer|counter4:u3|zero_detect:u0|Equal0~5                                                      ; |timer|counter4:u3|zero_detect:u0|Equal0~5                                                      ; out0             ;
; |timer|counter4:u3|bcd7:u1|lpm_mux:Mux6|mux_5fc:auto_generated|_~0                              ; |timer|counter4:u3|bcd7:u1|lpm_mux:Mux6|mux_5fc:auto_generated|_~0                              ; out0             ;
; |timer|counter4:u3|bcd7:u1|lpm_mux:Mux6|mux_5fc:auto_generated|_~1                              ; |timer|counter4:u3|bcd7:u1|lpm_mux:Mux6|mux_5fc:auto_generated|_~1                              ; out0             ;
; |timer|counter4:u3|bcd7:u1|lpm_mux:Mux6|mux_5fc:auto_generated|result_node[0]~0                 ; |timer|counter4:u3|bcd7:u1|lpm_mux:Mux6|mux_5fc:auto_generated|result_node[0]~0                 ; out0             ;
; |timer|counter4:u3|bcd7:u1|lpm_mux:Mux6|mux_5fc:auto_generated|_~2                              ; |timer|counter4:u3|bcd7:u1|lpm_mux:Mux6|mux_5fc:auto_generated|_~2                              ; out0             ;
; |timer|counter4:u3|bcd7:u1|lpm_mux:Mux6|mux_5fc:auto_generated|_~3                              ; |timer|counter4:u3|bcd7:u1|lpm_mux:Mux6|mux_5fc:auto_generated|_~3                              ; out0             ;
; |timer|counter4:u3|bcd7:u1|lpm_mux:Mux6|mux_5fc:auto_generated|result_node[0]~1                 ; |timer|counter4:u3|bcd7:u1|lpm_mux:Mux6|mux_5fc:auto_generated|result_node[0]~1                 ; out0             ;
; |timer|counter4:u3|bcd7:u1|lpm_mux:Mux6|mux_5fc:auto_generated|result_node[0]                   ; |timer|counter4:u3|bcd7:u1|lpm_mux:Mux6|mux_5fc:auto_generated|result_node[0]                   ; out0             ;
; |timer|counter4:u3|bcd7:u1|lpm_mux:Mux6|mux_5fc:auto_generated|_~4                              ; |timer|counter4:u3|bcd7:u1|lpm_mux:Mux6|mux_5fc:auto_generated|_~4                              ; out0             ;
; |timer|counter4:u3|bcd7:u1|lpm_mux:Mux6|mux_5fc:auto_generated|_~5                              ; |timer|counter4:u3|bcd7:u1|lpm_mux:Mux6|mux_5fc:auto_generated|_~5                              ; out0             ;
; |timer|counter4:u3|bcd7:u1|lpm_mux:Mux6|mux_5fc:auto_generated|_~6                              ; |timer|counter4:u3|bcd7:u1|lpm_mux:Mux6|mux_5fc:auto_generated|_~6                              ; out0             ;
; |timer|counter4:u3|bcd7:u1|lpm_mux:Mux6|mux_5fc:auto_generated|w_result112w~0                   ; |timer|counter4:u3|bcd7:u1|lpm_mux:Mux6|mux_5fc:auto_generated|w_result112w~0                   ; out0             ;
; |timer|counter4:u3|bcd7:u1|lpm_mux:Mux6|mux_5fc:auto_generated|w_result112w~1                   ; |timer|counter4:u3|bcd7:u1|lpm_mux:Mux6|mux_5fc:auto_generated|w_result112w~1                   ; out0             ;
; |timer|counter4:u3|bcd7:u1|lpm_mux:Mux6|mux_5fc:auto_generated|w_result112w                     ; |timer|counter4:u3|bcd7:u1|lpm_mux:Mux6|mux_5fc:auto_generated|w_result112w                     ; out0             ;
; |timer|counter4:u3|bcd7:u1|lpm_mux:Mux6|mux_5fc:auto_generated|_~8                              ; |timer|counter4:u3|bcd7:u1|lpm_mux:Mux6|mux_5fc:auto_generated|_~8                              ; out0             ;