counter4.tan.rpt

该芯片的功能是： ① 有一复位开关

; N/A   ; None         ; 8.564 ns   ; dual_reg4:u3|q[2] ; segs[7] ; clk        ;
; N/A   ; None         ; 7.684 ns   ; dual_reg4:u3|q[0] ; segs[6] ; clk        ;
; N/A   ; None         ; 7.683 ns   ; dual_reg4:u3|q[0] ; segs[3] ; clk        ;
; N/A   ; None         ; 7.676 ns   ; dual_reg4:u3|q[0] ; segs[4] ; clk        ;
; N/A   ; None         ; 7.665 ns   ; dual_reg4:u3|q[0] ; segs[1] ; clk        ;
; N/A   ; None         ; 7.659 ns   ; dual_reg4:u3|q[2] ; segs[3] ; clk        ;
; N/A   ; None         ; 7.659 ns   ; dual_reg4:u3|q[2] ; segs[6] ; clk        ;
; N/A   ; None         ; 7.653 ns   ; dual_reg4:u3|q[1] ; segs[7] ; clk        ;
; N/A   ; None         ; 7.652 ns   ; dual_reg4:u3|q[2] ; segs[4] ; clk        ;
; N/A   ; None         ; 7.640 ns   ; dual_reg4:u3|q[2] ; segs[1] ; clk        ;
; N/A   ; None         ; 7.608 ns   ; dual_reg4:u3|q[0] ; segs[7] ; clk        ;
; N/A   ; None         ; 7.594 ns   ; dual_reg4:u3|q[1] ; segs[4] ; clk        ;
; N/A   ; None         ; 7.591 ns   ; dual_reg4:u3|q[1] ; segs[6] ; clk        ;
; N/A   ; None         ; 7.587 ns   ; dual_reg4:u3|q[1] ; segs[3] ; clk        ;
; N/A   ; None         ; 7.575 ns   ; dual_reg4:u3|q[1] ; segs[1] ; clk        ;
; N/A   ; None         ; 7.549 ns   ; dual_reg4:u3|q[3] ; segs[7] ; clk        ;
; N/A   ; None         ; 7.506 ns   ; dual_reg4:u3|q[3] ; segs[4] ; clk        ;
; N/A   ; None         ; 7.504 ns   ; dual_reg4:u3|q[3] ; segs[6] ; clk        ;
; N/A   ; None         ; 7.499 ns   ; dual_reg4:u3|q[3] ; segs[3] ; clk        ;
; N/A   ; None         ; 7.488 ns   ; dual_reg4:u3|q[3] ; segs[1] ; clk        ;
; N/A   ; None         ; 7.453 ns   ; dual_reg4:u3|q[3] ; zero    ; clk        ;
; N/A   ; None         ; 7.347 ns   ; dual_reg4:u3|q[1] ; zero    ; clk        ;
; N/A   ; None         ; 7.273 ns   ; dual_reg4:u3|q[0] ; zero    ; clk        ;
; N/A   ; None         ; 7.270 ns   ; dual_reg4:u3|q[0] ; segs[2] ; clk        ;
; N/A   ; None         ; 7.269 ns   ; dual_reg4:u3|q[0] ; segs[5] ; clk        ;
; N/A   ; None         ; 7.246 ns   ; dual_reg4:u3|q[2] ; segs[2] ; clk        ;
; N/A   ; None         ; 7.245 ns   ; dual_reg4:u3|q[2] ; segs[5] ; clk        ;
; N/A   ; None         ; 7.184 ns   ; dual_reg4:u3|q[1] ; segs[5] ; clk        ;
; N/A   ; None         ; 7.182 ns   ; dual_reg4:u3|q[1] ; segs[2] ; clk        ;
; N/A   ; None         ; 7.133 ns   ; dual_reg4:u3|q[2] ; zero    ; clk        ;
; N/A   ; None         ; 7.096 ns   ; dual_reg4:u3|q[3] ; segs[5] ; clk        ;
; N/A   ; None         ; 7.094 ns   ; dual_reg4:u3|q[3] ; segs[2] ; clk        ;
+-------+--------------+------------+-------------------+---------+------------+


+-------------------------------------------------------------------------------------+
; th                                                                                  ;
+---------------+-------------+-----------+------------+-------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From       ; To                ; To Clock ;
+---------------+-------------+-----------+------------+-------------------+----------+
; N/A           ; None        ; -1.766 ns ; data_in[2] ; dual_reg4:u3|q[2] ; clk      ;
; N/A           ; None        ; -1.766 ns ; data_in[3] ; dual_reg4:u3|q[3] ; clk      ;
; N/A           ; None        ; -1.890 ns ; load       ; dual_reg4:u3|q[0] ; clk      ;
; N/A           ; None        ; -2.096 ns ; data_in[1] ; dual_reg4:u3|q[1] ; clk      ;
; N/A           ; None        ; -2.213 ns ; data_in[0] ; dual_reg4:u3|q[0] ; clk      ;
; N/A           ; None        ; -2.215 ns ; cnt_f_5    ; dual_reg4:u3|q[2] ; clk      ;
; N/A           ; None        ; -2.218 ns ; cnt_f_5    ; dual_reg4:u3|q[3] ; clk      ;
; N/A           ; None        ; -2.252 ns ; load       ; dual_reg4:u3|q[1] ; clk      ;
; N/A           ; None        ; -2.567 ns ; load       ; dual_reg4:u3|q[3] ; clk      ;
; N/A           ; None        ; -2.567 ns ; load       ; dual_reg4:u3|q[2] ; clk      ;
; N/A           ; None        ; -3.130 ns ; down       ; dual_reg4:u3|q[3] ; clk      ;
; N/A           ; None        ; -3.130 ns ; down       ; dual_reg4:u3|q[2] ; clk      ;
; N/A           ; None        ; -3.130 ns ; down       ; dual_reg4:u3|q[1] ; clk      ;
; N/A           ; None        ; -3.130 ns ; down       ; dual_reg4:u3|q[0] ; clk      ;
+---------------+-------------+-----------+------------+-------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Wed Sep 26 21:28:19 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off counter4 -c counter4 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 422.12 MHz between source register "dual_reg4:u3|q[3]" and destination register "dual_reg4:u3|q[3]"
    Info: fmax restricted to clock pin edge rate 2.369 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.571 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y1_N7; Fanout = 9; REG Node = 'dual_reg4:u3|q[3]'
            Info: 2: + IC(0.427 ns) + CELL(0.366 ns) = 0.793 ns; Loc. = LC_X2_Y1_N1; Fanout = 4; COMB Node = 'zero_detect:u0|Equal0~21'
            Info: 3: + IC(0.320 ns) + CELL(0.458 ns) = 1.571 ns; Loc. = LC_X2_Y1_N7; Fanout = 9; REG Node = 'dual_reg4:u3|q[3]'
            Info: Total cell delay = 0.824 ns ( 52.45 % )
            Info: Total interconnect delay = 0.747 ns ( 47.55 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 3.009 ns
                Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 4; CLK Node = 'clk'
                Info: 2: + IC(1.639 ns) + CELL(0.542 ns) = 3.009 ns; Loc. = LC_X2_Y1_N7; Fanout = 9; REG Node = 'dual_reg4:u3|q[3]'
                Info: Total cell delay = 1.370 ns ( 45.53 % )
                Info: Total interconnect delay = 1.639 ns ( 54.47 % )
            Info: - Longest clock path from clock "clk" to source register is 3.009 ns
                Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 4; CLK Node = 'clk'
                Info: 2: + IC(1.639 ns) + CELL(0.542 ns) = 3.009 ns; Loc. = LC_X2_Y1_N7; Fanout = 9; REG Node = 'dual_reg4:u3|q[3]'
                Info: Total cell delay = 1.370 ns ( 45.53 % )
                Info: Total interconnect delay = 1.639 ns ( 54.47 % )
        Info: + Micro clock to output delay of source is 0.156 ns
        Info: + Micro setup delay of destination is 0.010 ns
Info: tsu for register "dual_reg4:u3|q[3]" (data pin = "down", clock pin = "clk") is 3.240 ns
    Info: + Longest pin to register delay is 6.239 ns
        Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_Y21; Fanout = 1; PIN Node = 'down'
        Info: 2: + IC(3.667 ns) + CELL(0.280 ns) = 5.034 ns; Loc. = LC_X2_Y1_N0; Fanout = 4; COMB Node = 'dual_reg4:u3|q[0]~338'
        Info: 3: + IC(0.500 ns) + CELL(0.705 ns) = 6.239 ns; Loc. = LC_X2_Y1_N7; Fanout = 9; REG Node = 'dual_reg4:u3|q[3]'
        Info: Total cell delay = 2.072 ns ( 33.21 % )
        Info: Total interconnect delay = 4.167 ns ( 66.79 % )
    Info: + Micro setup delay of destination is 0.010 ns
    Info: - Shortest clock path from clock "clk" to destination register is 3.009 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(1.639 ns) + CELL(0.542 ns) = 3.009 ns; Loc. = LC_X2_Y1_N7; Fanout = 9; REG Node = 'dual_reg4:u3|q[3]'
        Info: Total cell delay = 1.370 ns ( 45.53 % )
        Info: Total interconnect delay = 1.639 ns ( 54.47 % )
Info: tco from clock "clk" to destination pin "segs[7]" through register "dual_reg4:u3|q[2]" is 8.564 ns
    Info: + Longest clock path from clock "clk" to source register is 3.009 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(1.639 ns) + CELL(0.542 ns) = 3.009 ns; Loc. = LC_X2_Y1_N2; Fanout = 10; REG Node = 'dual_reg4:u3|q[2]'
        Info: Total cell delay = 1.370 ns ( 45.53 % )
        Info: Total interconnect delay = 1.639 ns ( 54.47 % )
    Info: + Micro clock to output delay of source is 0.156 ns
    Info: + Longest register to pin delay is 5.399 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y1_N2; Fanout = 10; REG Node = 'dual_reg4:u3|q[2]'
        Info: 2: + IC(1.600 ns) + CELL(0.280 ns) = 1.880 ns; Loc. = LC_X2_Y1_N4; Fanout = 1; COMB Node = 'bcd7:u1|Mux6~27'
        Info: 3: + IC(1.115 ns) + CELL(2.404 ns) = 5.399 ns; Loc. = PIN_W19; Fanout = 0; PIN Node = 'segs[7]'
        Info: Total cell delay = 2.684 ns ( 49.71 % )
        Info: Total interconnect delay = 2.715 ns ( 50.29 % )
Info: th for register "dual_reg4:u3|q[2]" (data pin = "data_in[2]", clock pin = "clk") is -1.766 ns
    Info: + Longest clock path from clock "clk" to destination register is 3.009 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(1.639 ns) + CELL(0.542 ns) = 3.009 ns; Loc. = LC_X2_Y1_N2; Fanout = 10; REG Node = 'dual_reg4:u3|q[2]'
        Info: Total cell delay = 1.370 ns ( 45.53 % )
        Info: Total interconnect delay = 1.639 ns ( 54.47 % )
    Info: + Micro hold delay of destination is 0.100 ns
    Info: - Shortest pin to register delay is 4.875 ns
        Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_Y19; Fanout = 1; PIN Node = 'data_in[2]'
        Info: 2: + IC(3.703 ns) + CELL(0.085 ns) = 4.875 ns; Loc. = LC_X2_Y1_N2; Fanout = 10; REG Node = 'dual_reg4:u3|q[2]'
        Info: Total cell delay = 1.172 ns ( 24.04 % )
        Info: Total interconnect delay = 3.703 ns ( 75.96 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 100 megabytes of memory during processing
    Info: Processing ended: Wed Sep 26 21:28:20 2007
    Info: Elapsed time: 00:00:01