counter4.tan.qmsg

该芯片的功能是： ① 有一复位开关

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register dual_reg4:u3\|q\[3\] dual_reg4:u3\|q\[3\] 422.12 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 422.12 MHz between source register \"dual_reg4:u3\|q\[3\]\" and destination register \"dual_reg4:u3\|q\[3\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.369 ns " "Info: fmax restricted to clock pin edge rate 2.369 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.571 ns + Longest register register " "Info: + Longest register to register delay is 1.571 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns dual_reg4:u3\|q\[3\] 1 REG LC_X2_Y1_N7 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y1_N7; Fanout = 9; REG Node = 'dual_reg4:u3\|q\[3\]'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { dual_reg4:u3|q[3] } "NODE_NAME" } } { "dual_reg4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器芯片/dual_reg4.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.427 ns) + CELL(0.366 ns) 0.793 ns zero_detect:u0\|Equal0~21 2 COMB LC_X2_Y1_N1 4 " "Info: 2: + IC(0.427 ns) + CELL(0.366 ns) = 0.793 ns; Loc. = LC_X2_Y1_N1; Fanout = 4; COMB Node = 'zero_detect:u0\|Equal0~21'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.793 ns" { dual_reg4:u3|q[3] zero_detect:u0|Equal0~21 } "NODE_NAME" } } { "zero_detect.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器芯片/zero_detect.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.320 ns) + CELL(0.458 ns) 1.571 ns dual_reg4:u3\|q\[3\] 3 REG LC_X2_Y1_N7 9 " "Info: 3: + IC(0.320 ns) + CELL(0.458 ns) = 1.571 ns; Loc. = LC_X2_Y1_N7; Fanout = 9; REG Node = 'dual_reg4:u3\|q\[3\]'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.778 ns" { zero_detect:u0|Equal0~21 dual_reg4:u3|q[3] } "NODE_NAME" } } { "dual_reg4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器芯片/dual_reg4.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.824 ns ( 52.45 % ) " "Info: Total cell delay = 0.824 ns ( 52.45 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.747 ns ( 47.55 % ) " "Info: Total interconnect delay = 0.747 ns ( 47.55 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.571 ns" { dual_reg4:u3|q[3] zero_detect:u0|Equal0~21 dual_reg4:u3|q[3] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "1.571 ns" { dual_reg4:u3|q[3] zero_detect:u0|Equal0~21 dual_reg4:u3|q[3] } { 0.000ns 0.427ns 0.320ns } { 0.000ns 0.366ns 0.458ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.009 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.009 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 4 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 4; CLK Node = 'clk'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "counter4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器芯片/counter4.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.639 ns) + CELL(0.542 ns) 3.009 ns dual_reg4:u3\|q\[3\] 2 REG LC_X2_Y1_N7 9 " "Info: 2: + IC(1.639 ns) + CELL(0.542 ns) = 3.009 ns; Loc. = LC_X2_Y1_N7; Fanout = 9; REG Node = 'dual_reg4:u3\|q\[3\]'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.181 ns" { clk dual_reg4:u3|q[3] } "NODE_NAME" } } { "dual_reg4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器芯片/dual_reg4.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 45.53 % ) " "Info: Total cell delay = 1.370 ns ( 45.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.639 ns ( 54.47 % ) " "Info: Total interconnect delay = 1.639 ns ( 54.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.009 ns" { clk dual_reg4:u3|q[3] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "3.009 ns" { clk clk~out0 dual_reg4:u3|q[3] } { 0.000ns 0.000ns 1.639ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.009 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.009 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 4 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 4; CLK Node = 'clk'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "counter4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器芯片/counter4.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.639 ns) + CELL(0.542 ns) 3.009 ns dual_reg4:u3\|q\[3\] 2 REG LC_X2_Y1_N7 9 " "Info: 2: + IC(1.639 ns) + CELL(0.542 ns) = 3.009 ns; Loc. = LC_X2_Y1_N7; Fanout = 9; REG Node = 'dual_reg4:u3\|q\[3\]'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.181 ns" { clk dual_reg4:u3|q[3] } "NODE_NAME" } } { "dual_reg4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器芯片/dual_reg4.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 45.53 % ) " "Info: Total cell delay = 1.370 ns ( 45.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.639 ns ( 54.47 % ) " "Info: Total interconnect delay = 1.639 ns ( 54.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.009 ns" { clk dual_reg4:u3|q[3] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "3.009 ns" { clk clk~out0 dual_reg4:u3|q[3] } { 0.000ns 0.000ns 1.639ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.009 ns" { clk dual_reg4:u3|q[3] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "3.009 ns" { clk clk~out0 dual_reg4:u3|q[3] } { 0.000ns 0.000ns 1.639ns } { 0.000ns 0.828ns 0.542ns } "" } } { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.009 ns" { clk dual_reg4:u3|q[3] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "3.009 ns" { clk clk~out0 dual_reg4:u3|q[3] } { 0.000ns 0.000ns 1.639ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "dual_reg4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器芯片/dual_reg4.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "dual_reg4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器芯片/dual_reg4.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.571 ns" { dual_reg4:u3|q[3] zero_detect:u0|Equal0~21 dual_reg4:u3|q[3] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "1.571 ns" { dual_reg4:u3|q[3] zero_detect:u0|Equal0~21 dual_reg4:u3|q[3] } { 0.000ns 0.427ns 0.320ns } { 0.000ns 0.366ns 0.458ns } "" } } { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.009 ns" { clk dual_reg4:u3|q[3] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "3.009 ns" { clk clk~out0 dual_reg4:u3|q[3] } { 0.000ns 0.000ns 1.639ns } { 0.000ns 0.828ns 0.542ns } "" } } { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.009 ns" { clk dual_reg4:u3|q[3] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "3.009 ns" { clk clk~out0 dual_reg4:u3|q[3] } { 0.000ns 0.000ns 1.639ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { dual_reg4:u3|q[3] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { dual_reg4:u3|q[3] } {  } {  } "" } } { "dual_reg4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器芯片/dual_reg4.vhd" 21 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "dual_reg4:u3\|q\[3\] down clk 3.240 ns register " "Info: tsu for register \"dual_reg4:u3\|q\[3\]\" (data pin = \"down\", clock pin = \"clk\") is 3.240 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.239 ns + Longest pin register " "Info: + Longest pin to register delay is 6.239 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns down 1 PIN PIN_Y21 1 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_Y21; Fanout = 1; PIN Node = 'down'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { down } "NODE_NAME" } } { "counter4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器芯片/counter4.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.667 ns) + CELL(0.280 ns) 5.034 ns dual_reg4:u3\|q\[0\]~338 2 COMB LC_X2_Y1_N0 4 " "Info: 2: + IC(3.667 ns) + CELL(0.280 ns) = 5.034 ns; Loc. = LC_X2_Y1_N0; Fanout = 4; COMB Node = 'dual_reg4:u3\|q\[0\]~338'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.947 ns" { down dual_reg4:u3|q[0]~338 } "NODE_NAME" } } { "dual_reg4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器芯片/dual_reg4.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.500 ns) + CELL(0.705 ns) 6.239 ns dual_reg4:u3\|q\[3\] 3 REG LC_X2_Y1_N7 9 " "Info: 3: + IC(0.500 ns) + CELL(0.705 ns) = 6.239 ns; Loc. = LC_X2_Y1_N7; Fanout = 9; REG Node = 'dual_reg4:u3\|q\[3\]'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.205 ns" { dual_reg4:u3|q[0]~338 dual_reg4:u3|q[3] } "NODE_NAME" } } { "dual_reg4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器芯片/dual_reg4.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.072 ns ( 33.21 % ) " "Info: Total cell delay = 2.072 ns ( 33.21 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.167 ns ( 66.79 % ) " "Info: Total interconnect delay = 4.167 ns ( 66.79 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.239 ns" { down dual_reg4:u3|q[0]~338 dual_reg4:u3|q[3] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "6.239 ns" { down down~out0 dual_reg4:u3|q[0]~338 dual_reg4:u3|q[3] } { 0.000ns 0.000ns 3.667ns 0.500ns } { 0.000ns 1.087ns 0.280ns 0.705ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "dual_reg4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器芯片/dual_reg4.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.009 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.009 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 4 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 4; CLK Node = 'clk'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "counter4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器芯片/counter4.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.639 ns) + CELL(0.542 ns) 3.009 ns dual_reg4:u3\|q\[3\] 2 REG LC_X2_Y1_N7 9 " "Info: 2: + IC(1.639 ns) + CELL(0.542 ns) = 3.009 ns; Loc. = LC_X2_Y1_N7; Fanout = 9; REG Node = 'dual_reg4:u3\|q\[3\]'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.181 ns" { clk dual_reg4:u3|q[3] } "NODE_NAME" } } { "dual_reg4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器芯片/dual_reg4.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 45.53 % ) " "Info: Total cell delay = 1.370 ns ( 45.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.639 ns ( 54.47 % ) " "Info: Total interconnect delay = 1.639 ns ( 54.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.009 ns" { clk dual_reg4:u3|q[3] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "3.009 ns" { clk clk~out0 dual_reg4:u3|q[3] } { 0.000ns 0.000ns 1.639ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.239 ns" { down dual_reg4:u3|q[0]~338 dual_reg4:u3|q[3] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "6.239 ns" { down down~out0 dual_reg4:u3|q[0]~338 dual_reg4:u3|q[3] } { 0.000ns 0.000ns 3.667ns 0.500ns } { 0.000ns 1.087ns 0.280ns 0.705ns } "" } } { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.009 ns" { clk dual_reg4:u3|q[3] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "3.009 ns" { clk clk~out0 dual_reg4:u3|q[3] } { 0.000ns 0.000ns 1.639ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk segs\[7\] dual_reg4:u3\|q\[2\] 8.564 ns register " "Info: tco from clock \"clk\" to destination pin \"segs\[7\]\" through register \"dual_reg4:u3\|q\[2\]\" is 8.564 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.009 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.009 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 4 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 4; CLK Node = 'clk'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "counter4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器芯片/counter4.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.639 ns) + CELL(0.542 ns) 3.009 ns dual_reg4:u3\|q\[2\] 2 REG LC_X2_Y1_N2 10 " "Info: 2: + IC(1.639 ns) + CELL(0.542 ns) = 3.009 ns; Loc. = LC_X2_Y1_N2; Fanout = 10; REG Node = 'dual_reg4:u3\|q\[2\]'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.181 ns" { clk dual_reg4:u3|q[2] } "NODE_NAME" } } { "dual_reg4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器芯片/dual_reg4.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 45.53 % ) " "Info: Total cell delay = 1.370 ns ( 45.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.639 ns ( 54.47 % ) " "Info: Total interconnect delay = 1.639 ns ( 54.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.009 ns" { clk dual_reg4:u3|q[2] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "3.009 ns" { clk clk~out0 dual_reg4:u3|q[2] } { 0.000ns 0.000ns 1.639ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "dual_reg4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器芯片/dual_reg4.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.399 ns + Longest register pin " "Info: + Longest register to pin delay is 5.399 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns dual_reg4:u3\|q\[2\] 1 REG LC_X2_Y1_N2 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y1_N2; Fanout = 10; REG Node = 'dual_reg4:u3\|q\[2\]'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { dual_reg4:u3|q[2] } "NODE_NAME" } } { "dual_reg4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器芯片/dual_reg4.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(0.280 ns) 1.880 ns bcd7:u1\|Mux6~27 2 COMB LC_X2_Y1_N4 1 " "Info: 2: + IC(1.600 ns) + CELL(0.280 ns) = 1.880 ns; Loc. = LC_X2_Y1_N4; Fanout = 1; COMB Node = 'bcd7:u1\|Mux6~27'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.880 ns" { dual_reg4:u3|q[2] bcd7:u1|Mux6~27 } "NODE_NAME" } } { "bcd7.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器芯片/bcd7.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.115 ns) + CELL(2.404 ns) 5.399 ns segs\[7\] 3 PIN PIN_W19 0 " "Info: 3: + IC(1.115 ns) + CELL(2.404 ns) = 5.399 ns; Loc. = PIN_W19; Fanout = 0; PIN Node = 'segs\[7\]'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.519 ns" { bcd7:u1|Mux6~27 segs[7] } "NODE_NAME" } } { "counter4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器芯片/counter4.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.684 ns ( 49.71 % ) " "Info: Total cell delay = 2.684 ns ( 49.71 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.715 ns ( 50.29 % ) " "Info: Total interconnect delay = 2.715 ns ( 50.29 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.399 ns" { dual_reg4:u3|q[2] bcd7:u1|Mux6~27 segs[7] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "5.399 ns" { dual_reg4:u3|q[2] bcd7:u1|Mux6~27 segs[7] } { 0.000ns 1.600ns 1.115ns } { 0.000ns 0.280ns 2.404ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.009 ns" { clk dual_reg4:u3|q[2] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "3.009 ns" { clk clk~out0 dual_reg4:u3|q[2] } { 0.000ns 0.000ns 1.639ns } { 0.000ns 0.828ns 0.542ns } "" } } { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.399 ns" { dual_reg4:u3|q[2] bcd7:u1|Mux6~27 segs[7] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "5.399 ns" { dual_reg4:u3|q[2] bcd7:u1|Mux6~27 segs[7] } { 0.000ns 1.600ns 1.115ns } { 0.000ns 0.280ns 2.404ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "dual_reg4:u3\|q\[2\] data_in\[2\] clk -1.766 ns register " "Info: th for register \"dual_reg4:u3\|q\[2\]\" (data pin = \"data_in\[2\]\", clock pin = \"clk\") is -1.766 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.009 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 3.009 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 4 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 4; CLK Node = 'clk'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "counter4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器芯片/counter4.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.639 ns) + CELL(0.542 ns) 3.009 ns dual_reg4:u3\|q\[2\] 2 REG LC_X2_Y1_N2 10 " "Info: 2: + IC(1.639 ns) + CELL(0.542 ns) = 3.009 ns; Loc. = LC_X2_Y1_N2; Fanout = 10; REG Node = 'dual_reg4:u3\|q\[2\]'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.181 ns" { clk dual_reg4:u3|q[2] } "NODE_NAME" } } { "dual_reg4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器芯片/dual_reg4.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 45.53 % ) " "Info: Total cell delay = 1.370 ns ( 45.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.639 ns ( 54.47 % ) " "Info: Total interconnect delay = 1.639 ns ( 54.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.009 ns" { clk dual_reg4:u3|q[2] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "3.009 ns" { clk clk~out0 dual_reg4:u3|q[2] } { 0.000ns 0.000ns 1.639ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" {  } { { "dual_reg4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器芯片/dual_reg4.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.875 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.875 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns data_in\[2\] 1 PIN PIN_Y19 1 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_Y19; Fanout = 1; PIN Node = 'data_in\[2\]'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { data_in[2] } "NODE_NAME" } } { "counter4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器芯片/counter4.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.703 ns) + CELL(0.085 ns) 4.875 ns dual_reg4:u3\|q\[2\] 2 REG LC_X2_Y1_N2 10 " "Info: 2: + IC(3.703 ns) + CELL(0.085 ns) = 4.875 ns; Loc. = LC_X2_Y1_N2; Fanout = 10; REG Node = 'dual_reg4:u3\|q\[2\]'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.788 ns" { data_in[2] dual_reg4:u3|q[2] } "NODE_NAME" } } { "dual_reg4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器芯片/dual_reg4.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.172 ns ( 24.04 % ) " "Info: Total cell delay = 1.172 ns ( 24.04 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.703 ns ( 75.96 % ) " "Info: Total interconnect delay = 3.703 ns ( 75.96 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.875 ns" { data_in[2] dual_reg4:u3|q[2] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "4.875 ns" { data_in[2] data_in[2]~out0 dual_reg4:u3|q[2] } { 0.000ns 0.000ns 3.703ns } { 0.000ns 1.087ns 0.085ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.009 ns" { clk dual_reg4:u3|q[2] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "3.009 ns" { clk clk~out0 dual_reg4:u3|q[2] } { 0.000ns 0.000ns 1.639ns } { 0.000ns 0.828ns 0.542ns } "" } } { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.875 ns" { data_in[2] dual_reg4:u3|q[2] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "4.875 ns" { data_in[2] data_in[2]~out0 dual_reg4:u3|q[2] } { 0.000ns 0.000ns 3.703ns } { 0.000ns 1.087ns 0.085ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}