counter4.fnsim.qmsg

该芯片的功能是： ① 有一复位开关

{ "Info" "ISGN_MEGAFN_DESCENDANT" "decr4:u2\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:oflow_node decr4:u2\|lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"decr4:u2\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"decr4:u2\|lpm_add_sub:Add0\"" {  } { { "addcore.tdf" "" { Text "d:/program files/altera/70/quartus/libraries/megafunctions/addcore.tdf" 94 2 0 } } { "decr4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/定时器芯片/decr4.vhd" 13 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "decr4:u2\|lpm_add_sub:Add0 " "Info: Instantiated megafunction \"decr4:u2\|lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 5 " "Info: Parameter \"LPM_WIDTH\" = \"5\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } { { "decr4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/定时器芯片/decr4.vhd" 13 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "decr4:u2\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node decr4:u2\|lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"decr4:u2\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"decr4:u2\|lpm_add_sub:Add0\"" {  } { { "addcore.tdf" "" { Text "d:/program files/altera/70/quartus/libraries/megafunctions/addcore.tdf" 120 6 0 } } { "decr4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/定时器芯片/decr4.vhd" 13 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "decr4:u2\|lpm_add_sub:Add0 " "Info: Instantiated megafunction \"decr4:u2\|lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 5 " "Info: Parameter \"LPM_WIDTH\" = \"5\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } { { "decr4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/定时器芯片/decr4.vhd" 13 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "altshift.tdf" "" { Text "d:/program files/altera/70/quartus/libraries/megafunctions/altshift.tdf" 30 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "decr4:u2\|lpm_add_sub:Add0\|altshift:result_ext_latency_ffs decr4:u2\|lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"decr4:u2\|lpm_add_sub:Add0\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"decr4:u2\|lpm_add_sub:Add0\"" {  } { { "lpm_add_sub.tdf" "" { Text "d:/program files/altera/70/quartus/libraries/megafunctions/lpm_add_sub.tdf" 286 2 0 } } { "decr4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/定时器芯片/decr4.vhd" 13 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "decr4:u2\|lpm_add_sub:Add0 " "Info: Instantiated megafunction \"decr4:u2\|lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 5 " "Info: Parameter \"LPM_WIDTH\" = \"5\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } { { "decr4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/定时器芯片/decr4.vhd" 13 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "decr4:u2\|lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs decr4:u2\|lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"decr4:u2\|lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs\", which is child of megafunction instantiation \"decr4:u2\|lpm_add_sub:Add0\"" {  } { { "lpm_add_sub.tdf" "" { Text "d:/program files/altera/70/quartus/libraries/megafunctions/lpm_add_sub.tdf" 288 2 0 } } { "decr4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/定时器芯片/decr4.vhd" 13 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "decr4:u2\|lpm_add_sub:Add0 " "Info: Instantiated megafunction \"decr4:u2\|lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 5 " "Info: Parameter \"LPM_WIDTH\" = \"5\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } { { "decr4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/定时器芯片/decr4.vhd" 13 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../libraries/megafunctions/lpm_mux.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../libraries/megafunctions/lpm_mux.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_mux " "Info: Found entity 1: lpm_mux" {  } { { "lpm_mux.tdf" "" { Text "d:/program files/altera/70/quartus/libraries/megafunctions/lpm_mux.tdf" 74 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "bcd7:u1\|lpm_mux:Mux0 " "Info: Elaborated megafunction instantiation \"bcd7:u1\|lpm_mux:Mux0\"" {  } { { "bcd7.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/定时器芯片/bcd7.vhd" 11 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_5fc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/mux_5fc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_5fc " "Info: Found entity 1: mux_5fc" {  } { { "db/mux_5fc.tdf" "" { Text "D:/Program Files/altera/70/quartus/自己实践/定时器芯片/db/mux_5fc.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "bcd7:u1\|lpm_mux:Mux1 " "Info: Elaborated megafunction instantiation \"bcd7:u1\|lpm_mux:Mux1\"" {  } { { "bcd7.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/定时器芯片/bcd7.vhd" 11 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "bcd7:u1\|lpm_mux:Mux2 " "Info: Elaborated megafunction instantiation \"bcd7:u1\|lpm_mux:Mux2\"" {  } { { "bcd7.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/定时器芯片/bcd7.vhd" 11 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "bcd7:u1\|lpm_mux:Mux3 " "Info: Elaborated megafunction instantiation \"bcd7:u1\|lpm_mux:Mux3\"" {  } { { "bcd7.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/定时器芯片/bcd7.vhd" 11 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "bcd7:u1\|lpm_mux:Mux4 " "Info: Elaborated megafunction instantiation \"bcd7:u1\|lpm_mux:Mux4\"" {  } { { "bcd7.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/定时器芯片/bcd7.vhd" 11 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "bcd7:u1\|lpm_mux:Mux5 " "Info: Elaborated megafunction instantiation \"bcd7:u1\|lpm_mux:Mux5\"" {  } { { "bcd7.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/定时器芯片/bcd7.vhd" 11 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "bcd7:u1\|lpm_mux:Mux6 " "Info: Elaborated megafunction instantiation \"bcd7:u1\|lpm_mux:Mux6\"" {  } { { "bcd7.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/定时器芯片/bcd7.vhd" 11 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Functional Simulation Netlist Generation 0 s 1  Quartus II " "Info: Quartus II Functional Simulation Netlist Generation was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "137 " "Info: Allocated 137 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Sep 24 19:58:45 2007 " "Info: Processing ended: Mon Sep 24 19:58:45 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}