counter4.fnsim.qmsg

该芯片的功能是： ① 有一复位开关

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Functional Simulation Netlist Generation Quartus II " "Info: Running Quartus II Functional Simulation Netlist Generation" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Sep 24 19:58:40 2007 " "Info: Processing started: Mon Sep 24 19:58:40 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off counter4 -c counter4 --generate_functional_sim_netlist " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off counter4 -c counter4 --generate_functional_sim_netlist" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "D:/Program Files/altera/70/quartus/程序/定时器芯片/counter4.vhd " "Warning: Can't analyze file -- file D:/Program Files/altera/70/quartus/程序/定时器芯片/counter4.vhd is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "zero_detect.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file zero_detect.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 zero_detect-rtl " "Info: Found design unit 1: zero_detect-rtl" {  } { { "zero_detect.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/定时器芯片/zero_detect.vhd" 7 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 zero_detect " "Info: Found entity 1: zero_detect" {  } { { "zero_detect.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/定时器芯片/zero_detect.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "bcd7.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file bcd7.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 bcd7-rtl " "Info: Found design unit 1: bcd7-rtl" {  } { { "bcd7.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/定时器芯片/bcd7.vhd" 7 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 bcd7 " "Info: Found entity 1: bcd7" {  } { { "bcd7.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/定时器芯片/bcd7.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "decr4.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file decr4.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 decr4-rtl " "Info: Found design unit 1: decr4-rtl" {  } { { "decr4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/定时器芯片/decr4.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 decr4 " "Info: Found entity 1: decr4" {  } { { "decr4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/定时器芯片/decr4.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dual_reg4.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file dual_reg4.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 dual_reg4-rtl " "Info: Found design unit 1: dual_reg4-rtl" {  } { { "dual_reg4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/定时器芯片/dual_reg4.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 dual_reg4 " "Info: Found entity 1: dual_reg4" {  } { { "dual_reg4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/定时器芯片/dual_reg4.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "counter4.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file counter4.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 counter4-structure " "Info: Found design unit 1: counter4-structure" {  } { { "counter4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/定时器芯片/counter4.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 counter4 " "Info: Found entity 1: counter4" {  } { { "counter4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/定时器芯片/counter4.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "counter4 " "Info: Elaborating entity \"counter4\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "zero_detect zero_detect:u0 " "Info: Elaborating entity \"zero_detect\" for hierarchy \"zero_detect:u0\"" {  } { { "counter4.vhd" "u0" { Text "D:/Program Files/altera/70/quartus/自己实践/定时器芯片/counter4.vhd" 38 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bcd7 bcd7:u1 " "Info: Elaborating entity \"bcd7\" for hierarchy \"bcd7:u1\"" {  } { { "counter4.vhd" "u1" { Text "D:/Program Files/altera/70/quartus/自己实践/定时器芯片/counter4.vhd" 40 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decr4 decr4:u2 " "Info: Elaborating entity \"decr4\" for hierarchy \"decr4:u2\"" {  } { { "counter4.vhd" "u2" { Text "D:/Program Files/altera/70/quartus/自己实践/定时器芯片/counter4.vhd" 42 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dual_reg4 dual_reg4:u3 " "Info: Elaborating entity \"dual_reg4\" for hierarchy \"dual_reg4:u3\"" {  } { { "counter4.vhd" "u3" { Text "D:/Program Files/altera/70/quartus/自己实践/定时器芯片/counter4.vhd" 44 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "d:/program files/altera/70/quartus/libraries/megafunctions/lpm_add_sub.tdf" 102 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "decr4:u2\|lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"decr4:u2\|lpm_add_sub:Add0\"" {  } { { "decr4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/定时器芯片/decr4.vhd" 13 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "d:/program files/altera/70/quartus/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "decr4:u2\|lpm_add_sub:Add0\|addcore:adder decr4:u2\|lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"decr4:u2\|lpm_add_sub:Add0\|addcore:adder\", which is child of megafunction instantiation \"decr4:u2\|lpm_add_sub:Add0\"" {  } { { "lpm_add_sub.tdf" "" { Text "d:/program files/altera/70/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 4 0 } } { "decr4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/定时器芯片/decr4.vhd" 13 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "decr4:u2\|lpm_add_sub:Add0 " "Info: Instantiated megafunction \"decr4:u2\|lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 5 " "Info: Parameter \"LPM_WIDTH\" = \"5\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } { { "decr4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/定时器芯片/decr4.vhd" 13 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "a_csnbuffer.tdf" "" { Text "d:/program files/altera/70/quartus/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}