counter4.map.qmsg

该芯片的功能是： ① 有一复位开关

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Sep 26 21:27:47 2007 " "Info: Processing started: Wed Sep 26 21:27:47 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off counter4 -c counter4 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off counter4 -c counter4" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "D:/Program Files/altera/70/quartus/程序/定时器芯片/counter4.vhd " "Warning: Can't analyze file -- file D:/Program Files/altera/70/quartus/程序/定时器芯片/counter4.vhd is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "zero_detect.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file zero_detect.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 zero_detect-rtl " "Info: Found design unit 1: zero_detect-rtl" {  } { { "zero_detect.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器芯片/zero_detect.vhd" 7 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 zero_detect " "Info: Found entity 1: zero_detect" {  } { { "zero_detect.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器芯片/zero_detect.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "bcd7.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file bcd7.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 bcd7-rtl " "Info: Found design unit 1: bcd7-rtl" {  } { { "bcd7.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器芯片/bcd7.vhd" 7 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 bcd7 " "Info: Found entity 1: bcd7" {  } { { "bcd7.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器芯片/bcd7.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "decr4.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file decr4.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 decr4-rtl " "Info: Found design unit 1: decr4-rtl" {  } { { "decr4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器芯片/decr4.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 decr4 " "Info: Found entity 1: decr4" {  } { { "decr4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器芯片/decr4.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dual_reg4.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file dual_reg4.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 dual_reg4-rtl " "Info: Found design unit 1: dual_reg4-rtl" {  } { { "dual_reg4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器芯片/dual_reg4.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 dual_reg4 " "Info: Found entity 1: dual_reg4" {  } { { "dual_reg4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器芯片/dual_reg4.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "counter4.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file counter4.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 counter4-structure " "Info: Found design unit 1: counter4-structure" {  } { { "counter4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器芯片/counter4.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 counter4 " "Info: Found entity 1: counter4" {  } { { "counter4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器芯片/counter4.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "state_control.vhd 3 1 " "Info: Found 3 design units, including 1 entities, in source file state_control.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 state_pack " "Info: Found design unit 1: state_pack" {  } { { "state_control.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器芯片/state_control.vhd" 3 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 state_control-state_control_arc " "Info: Found design unit 2: state_control-state_control_arc" {  } { { "state_control.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器芯片/state_control.vhd" 21 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 state_control " "Info: Found entity 1: state_control" {  } { { "state_control.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器芯片/state_control.vhd" 9 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "counter4 " "Info: Elaborating entity \"counter4\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "zero_detect zero_detect:u0 " "Info: Elaborating entity \"zero_detect\" for hierarchy \"zero_detect:u0\"" {  } { { "counter4.vhd" "u0" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器芯片/counter4.vhd" 38 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bcd7 bcd7:u1 " "Info: Elaborating entity \"bcd7\" for hierarchy \"bcd7:u1\"" {  } { { "counter4.vhd" "u1" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器芯片/counter4.vhd" 40 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decr4 decr4:u2 " "Info: Elaborating entity \"decr4\" for hierarchy \"decr4:u2\"" {  } { { "counter4.vhd" "u2" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器芯片/counter4.vhd" 42 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dual_reg4 dual_reg4:u3 " "Info: Elaborating entity \"dual_reg4\" for hierarchy \"dual_reg4:u3\"" {  } { { "counter4.vhd" "u3" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器芯片/counter4.vhd" 44 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "38 " "Info: Implemented 38 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "8 " "Info: Implemented 8 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "8 " "Info: Implemented 8 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "22 " "Info: Implemented 22 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "140 " "Info: Allocated 140 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 26 21:27:50 2007 " "Info: Processing ended: Wed Sep 26 21:27:50 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}