counter4.map.rpt

该芯片的功能是： ① 有一复位开关

; zero_detect.vhd                  ; yes             ; User VHDL File  ; D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器芯片/zero_detect.vhd ;
; bcd7.vhd                         ; yes             ; User VHDL File  ; D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器芯片/bcd7.vhd        ;
; decr4.vhd                        ; yes             ; User VHDL File  ; D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器芯片/decr4.vhd       ;
; dual_reg4.vhd                    ; yes             ; User VHDL File  ; D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器芯片/dual_reg4.vhd   ;
; counter4.vhd                     ; yes             ; User VHDL File  ; D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/定时器芯片/counter4.vhd    ;
+----------------------------------+-----------------+-----------------+-----------------------------------------------------------------------------------------+


+-----------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                     ;
+---------------------------------------------+-------------------+
; Resource                                    ; Usage             ;
+---------------------------------------------+-------------------+
; Total logic elements                        ; 22                ;
;     -- Combinational with no register       ; 18                ;
;     -- Register only                        ; 0                 ;
;     -- Combinational with a register        ; 4                 ;
;                                             ;                   ;
; Logic element usage by number of LUT inputs ;                   ;
;     -- 4 input functions                    ; 10                ;
;     -- 3 input functions                    ; 4                 ;
;     -- 2 input functions                    ; 2                 ;
;     -- 1 input functions                    ; 6                 ;
;     -- 0 input functions                    ; 0                 ;
;                                             ;                   ;
; Logic elements by mode                      ;                   ;
;     -- normal mode                          ; 22                ;
;     -- arithmetic mode                      ; 0                 ;
;     -- qfbk mode                            ; 0                 ;
;     -- register cascade mode                ; 0                 ;
;     -- synchronous clear/load mode          ; 2                 ;
;     -- asynchronous clear/load mode         ; 0                 ;
;                                             ;                   ;
; Total registers                             ; 4                 ;
; I/O pins                                    ; 0                 ;
; Maximum fan-out node                        ; dual_reg4:u3|q[0] ;
; Maximum fan-out                             ; 12                ;
; Total fan-out                               ; 82                ;
; Average fan-out                             ; 2.16              ;
+---------------------------------------------+-------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                          ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+--------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name      ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+--------------------------+
; |counter4                  ; 22 (0)      ; 4            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 18 (0)       ; 0 (0)             ; 4 (0)            ; 0 (0)           ; 0 (0)      ; |counter4                ;
;    |bcd7:u1|               ; 13 (13)     ; 0            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 13 (13)      ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |counter4|bcd7:u1        ;
;    |decr4:u2|              ; 2 (2)       ; 0            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |counter4|decr4:u2       ;
;    |dual_reg4:u3|          ; 6 (6)       ; 4            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 4 (4)            ; 0 (0)           ; 0 (0)      ; |counter4|dual_reg4:u3   ;
;    |zero_detect:u0|        ; 1 (1)       ; 0            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |counter4|zero_detect:u0 ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+--------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 4     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 2     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 4     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                            ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output  ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------+
; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |counter4|dual_reg4:u3|q[0] ;
; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |counter4|dual_reg4:u3|q[2] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Wed Sep 26 21:27:47 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off counter4 -c counter4
Warning: Can't analyze file -- file D:/Program Files/altera/70/quartus/程序/定时器芯片/counter4.vhd is missing
Info: Found 2 design units, including 1 entities, in source file zero_detect.vhd
    Info: Found design unit 1: zero_detect-rtl
    Info: Found entity 1: zero_detect
Info: Found 2 design units, including 1 entities, in source file bcd7.vhd
    Info: Found design unit 1: bcd7-rtl
    Info: Found entity 1: bcd7
Info: Found 2 design units, including 1 entities, in source file decr4.vhd
    Info: Found design unit 1: decr4-rtl
    Info: Found entity 1: decr4
Info: Found 2 design units, including 1 entities, in source file dual_reg4.vhd
    Info: Found design unit 1: dual_reg4-rtl
    Info: Found entity 1: dual_reg4
Info: Found 2 design units, including 1 entities, in source file counter4.vhd
    Info: Found design unit 1: counter4-structure
    Info: Found entity 1: counter4
Info: Found 3 design units, including 1 entities, in source file state_control.vhd
    Info: Found design unit 1: state_pack
    Info: Found design unit 2: state_control-state_control_arc
    Info: Found entity 1: state_control
Info: Elaborating entity "counter4" for the top level hierarchy
Info: Elaborating entity "zero_detect" for hierarchy "zero_detect:u0"
Info: Elaborating entity "bcd7" for hierarchy "bcd7:u1"
Info: Elaborating entity "decr4" for hierarchy "decr4:u2"
Info: Elaborating entity "dual_reg4" for hierarchy "dual_reg4:u3"
Info: Implemented 38 device resources after synthesis - the final resource count might be different
    Info: Implemented 8 input pins
    Info: Implemented 8 output pins
    Info: Implemented 22 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning
    Info: Allocated 140 megabytes of memory during processing
    Info: Processing ended: Wed Sep 26 21:27:50 2007
    Info: Elapsed time: 00:00:03