loader.map.qmsg

该芯片的功能是： ① 有一复位开关

{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "load_val\[14\] loader.vhd(14) " "Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for \"load_val\[14\]\"" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/程序/微波炉定时器芯片/数据装入器/loader.vhd" 14 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "load_val\[15\] loader.vhd(14) " "Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for \"load_val\[15\]\"" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/程序/微波炉定时器芯片/数据装入器/loader.vhd" 14 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "load_val\[0\]\$latch " "Warning: Latch load_val\[0\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA load_done " "Warning: Ports D and ENA on the latch are fed by the same signal load_done" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/程序/微波炉定时器芯片/数据装入器/loader.vhd" 8 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/程序/微波炉定时器芯片/数据装入器/loader.vhd" 14 0 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "load_val\[1\]\$latch " "Warning: Latch load_val\[1\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA load_clk " "Warning: Ports D and ENA on the latch are fed by the same signal load_clk" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/程序/微波炉定时器芯片/数据装入器/loader.vhd" 7 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/程序/微波炉定时器芯片/数据装入器/loader.vhd" 14 0 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "load_val\[2\]\$latch " "Warning: Latch load_val\[2\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA load_done " "Warning: Ports D and ENA on the latch are fed by the same signal load_done" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/程序/微波炉定时器芯片/数据装入器/loader.vhd" 8 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/程序/微波炉定时器芯片/数据装入器/loader.vhd" 14 0 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "load_val\[3\]\$latch " "Warning: Latch load_val\[3\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA load_clk " "Warning: Ports D and ENA on the latch are fed by the same signal load_clk" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/程序/微波炉定时器芯片/数据装入器/loader.vhd" 7 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/程序/微波炉定时器芯片/数据装入器/loader.vhd" 14 0 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "load_val\[4\]\$latch " "Warning: Latch load_val\[4\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA load_clk " "Warning: Ports D and ENA on the latch are fed by the same signal load_clk" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/程序/微波炉定时器芯片/数据装入器/loader.vhd" 7 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/程序/微波炉定时器芯片/数据装入器/loader.vhd" 14 0 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "load_val\[5\]\$latch " "Warning: Latch load_val\[5\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA load_clk " "Warning: Ports D and ENA on the latch are fed by the same signal load_clk" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/程序/微波炉定时器芯片/数据装入器/loader.vhd" 7 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/程序/微波炉定时器芯片/数据装入器/loader.vhd" 14 0 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "load_val\[6\]\$latch " "Warning: Latch load_val\[6\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA load_done " "Warning: Ports D and ENA on the latch are fed by the same signal load_done" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/程序/微波炉定时器芯片/数据装入器/loader.vhd" 8 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/程序/微波炉定时器芯片/数据装入器/loader.vhd" 14 0 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "load_val\[7\]\$latch " "Warning: Latch load_val\[7\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA load_clk " "Warning: Ports D and ENA on the latch are fed by the same signal load_clk" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/程序/微波炉定时器芯片/数据装入器/loader.vhd" 7 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/程序/微波炉定时器芯片/数据装入器/loader.vhd" 14 0 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "load_val\[8\]\$latch " "Warning: Latch load_val\[8\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA load_done " "Warning: Ports D and ENA on the latch are fed by the same signal load_done" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/程序/微波炉定时器芯片/数据装入器/loader.vhd" 8 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/程序/微波炉定时器芯片/数据装入器/loader.vhd" 14 0 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "load_val\[9\]\$latch " "Warning: Latch load_val\[9\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA load_done " "Warning: Ports D and ENA on the latch are fed by the same signal load_done" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/程序/微波炉定时器芯片/数据装入器/loader.vhd" 8 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/程序/微波炉定时器芯片/数据装入器/loader.vhd" 14 0 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "load_val\[10\]\$latch " "Warning: Latch load_val\[10\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA load_clk " "Warning: Ports D and ENA on the latch are fed by the same signal load_clk" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/程序/微波炉定时器芯片/数据装入器/loader.vhd" 7 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/程序/微波炉定时器芯片/数据装入器/loader.vhd" 14 0 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "load_val\[11\]\$latch " "Warning: Latch load_val\[11\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA load_clk " "Warning: Ports D and ENA on the latch are fed by the same signal load_clk" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/程序/微波炉定时器芯片/数据装入器/loader.vhd" 7 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/程序/微波炉定时器芯片/数据装入器/loader.vhd" 14 0 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "load_val\[12\]\$latch " "Warning: Latch load_val\[12\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA load_clk " "Warning: Ports D and ENA on the latch are fed by the same signal load_clk" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/程序/微波炉定时器芯片/数据装入器/loader.vhd" 7 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/程序/微波炉定时器芯片/数据装入器/loader.vhd" 14 0 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "load_val\[13\]\$latch " "Warning: Latch load_val\[13\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA load_done " "Warning: Ports D and ENA on the latch are fed by the same signal load_done" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/程序/微波炉定时器芯片/数据装入器/loader.vhd" 8 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/程序/微波炉定时器芯片/数据装入器/loader.vhd" 14 0 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "load_val\[14\]\$latch " "Warning: Latch load_val\[14\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA load_clk " "Warning: Ports D and ENA on the latch are fed by the same signal load_clk" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/程序/微波炉定时器芯片/数据装入器/loader.vhd" 7 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/程序/微波炉定时器芯片/数据装入器/loader.vhd" 14 0 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "load_val\[15\]\$latch " "Warning: Latch load_val\[15\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA load_clk " "Warning: Ports D and ENA on the latch are fed by the same signal load_clk" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/程序/微波炉定时器芯片/数据装入器/loader.vhd" 7 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/程序/微波炉定时器芯片/数据装入器/loader.vhd" 14 0 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "70 " "Info: Implemented 70 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "19 " "Info: Implemented 19 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "17 " "Info: Implemented 17 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "34 " "Info: Implemented 34 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 35 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 35 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "130 " "Info: Allocated 130 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 26 15:50:48 2007 " "Info: Processing ended: Wed Sep 26 15:50:48 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}