loader.map.qmsg

该芯片的功能是： ① 有一复位开关

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Sep 26 15:50:43 2007 " "Info: Processing started: Wed Sep 26 15:50:43 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off loader -c loader " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off loader -c loader" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/数据装入器/loader.vhd " "Warning: Can't analyze file -- file D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/数据装入器/loader.vhd is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "loader.vhd 2 1 " "Warning: Using design file loader.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 loader-loader_arc " "Info: Found design unit 1: loader-loader_arc" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/程序/微波炉定时器芯片/数据装入器/loader.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 loader " "Info: Found entity 1: loader" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/程序/微波炉定时器芯片/数据装入器/loader.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "loader " "Info: Elaborating entity \"loader\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "load_val loader.vhd(14) " "Warning (10631): VHDL Process Statement warning at loader.vhd(14): inferring latch(es) for signal or variable \"load_val\", which holds its previous value in one or more paths through the process" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/程序/微波炉定时器芯片/数据装入器/loader.vhd" 14 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "load_val\[0\] loader.vhd(14) " "Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for \"load_val\[0\]\"" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/程序/微波炉定时器芯片/数据装入器/loader.vhd" 14 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "load_val\[1\] loader.vhd(14) " "Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for \"load_val\[1\]\"" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/程序/微波炉定时器芯片/数据装入器/loader.vhd" 14 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "load_val\[2\] loader.vhd(14) " "Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for \"load_val\[2\]\"" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/程序/微波炉定时器芯片/数据装入器/loader.vhd" 14 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "load_val\[3\] loader.vhd(14) " "Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for \"load_val\[3\]\"" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/程序/微波炉定时器芯片/数据装入器/loader.vhd" 14 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "load_val\[4\] loader.vhd(14) " "Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for \"load_val\[4\]\"" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/程序/微波炉定时器芯片/数据装入器/loader.vhd" 14 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "load_val\[5\] loader.vhd(14) " "Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for \"load_val\[5\]\"" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/程序/微波炉定时器芯片/数据装入器/loader.vhd" 14 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "load_val\[6\] loader.vhd(14) " "Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for \"load_val\[6\]\"" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/程序/微波炉定时器芯片/数据装入器/loader.vhd" 14 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "load_val\[7\] loader.vhd(14) " "Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for \"load_val\[7\]\"" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/程序/微波炉定时器芯片/数据装入器/loader.vhd" 14 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "load_val\[8\] loader.vhd(14) " "Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for \"load_val\[8\]\"" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/程序/微波炉定时器芯片/数据装入器/loader.vhd" 14 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "load_val\[9\] loader.vhd(14) " "Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for \"load_val\[9\]\"" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/程序/微波炉定时器芯片/数据装入器/loader.vhd" 14 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "load_val\[10\] loader.vhd(14) " "Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for \"load_val\[10\]\"" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/程序/微波炉定时器芯片/数据装入器/loader.vhd" 14 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "load_val\[11\] loader.vhd(14) " "Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for \"load_val\[11\]\"" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/程序/微波炉定时器芯片/数据装入器/loader.vhd" 14 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "load_val\[12\] loader.vhd(14) " "Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for \"load_val\[12\]\"" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/程序/微波炉定时器芯片/数据装入器/loader.vhd" 14 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "load_val\[13\] loader.vhd(14) " "Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for \"load_val\[13\]\"" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/程序/微波炉定时器芯片/数据装入器/loader.vhd" 14 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}