loader.fnsim.qmsg

该芯片的功能是： ① 有一复位开关

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Functional Simulation Netlist Generation Quartus II " "Info: Running Quartus II Functional Simulation Netlist Generation" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Sep 26 21:25:34 2007 " "Info: Processing started: Wed Sep 26 21:25:34 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off loader -c loader --generate_functional_sim_netlist " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off loader -c loader --generate_functional_sim_netlist" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "loader.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file loader.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 loader-loader_arc " "Info: Found design unit 1: loader-loader_arc" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/数据装入器/loader.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 loader " "Info: Found entity 1: loader" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/数据装入器/loader.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "loader " "Info: Elaborating entity \"loader\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "load_val loader.vhd(14) " "Warning (10631): VHDL Process Statement warning at loader.vhd(14): inferring latch(es) for signal or variable \"load_val\", which holds its previous value in one or more paths through the process" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/数据装入器/loader.vhd" 14 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "load_val\[0\] loader.vhd(14) " "Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for \"load_val\[0\]\"" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/数据装入器/loader.vhd" 14 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "load_val\[1\] loader.vhd(14) " "Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for \"load_val\[1\]\"" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/数据装入器/loader.vhd" 14 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "load_val\[2\] loader.vhd(14) " "Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for \"load_val\[2\]\"" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/数据装入器/loader.vhd" 14 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "load_val\[3\] loader.vhd(14) " "Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for \"load_val\[3\]\"" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/数据装入器/loader.vhd" 14 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "load_val\[4\] loader.vhd(14) " "Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for \"load_val\[4\]\"" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/数据装入器/loader.vhd" 14 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "load_val\[5\] loader.vhd(14) " "Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for \"load_val\[5\]\"" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/数据装入器/loader.vhd" 14 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "load_val\[6\] loader.vhd(14) " "Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for \"load_val\[6\]\"" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/数据装入器/loader.vhd" 14 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "load_val\[7\] loader.vhd(14) " "Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for \"load_val\[7\]\"" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/数据装入器/loader.vhd" 14 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "load_val\[8\] loader.vhd(14) " "Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for \"load_val\[8\]\"" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/数据装入器/loader.vhd" 14 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "load_val\[9\] loader.vhd(14) " "Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for \"load_val\[9\]\"" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/数据装入器/loader.vhd" 14 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "load_val\[10\] loader.vhd(14) " "Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for \"load_val\[10\]\"" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/数据装入器/loader.vhd" 14 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "load_val\[11\] loader.vhd(14) " "Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for \"load_val\[11\]\"" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/数据装入器/loader.vhd" 14 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "load_val\[12\] loader.vhd(14) " "Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for \"load_val\[12\]\"" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/数据装入器/loader.vhd" 14 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "load_val\[13\] loader.vhd(14) " "Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for \"load_val\[13\]\"" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/数据装入器/loader.vhd" 14 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "load_val\[14\] loader.vhd(14) " "Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for \"load_val\[14\]\"" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/数据装入器/loader.vhd" 14 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "load_val\[15\] loader.vhd(14) " "Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for \"load_val\[15\]\"" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/数据装入器/loader.vhd" 14 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../libraries/megafunctions/lpm_mux.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../libraries/megafunctions/lpm_mux.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_mux " "Info: Found entity 1: lpm_mux" {  } { { "lpm_mux.tdf" "" { Text "d:/program files/altera/70/quartus/libraries/megafunctions/lpm_mux.tdf" 74 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mux:Mux0 " "Info: Elaborated megafunction instantiation \"lpm_mux:Mux0\"" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/数据装入器/loader.vhd" 21 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_ldc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/mux_ldc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_ldc " "Info: Found entity 1: mux_ldc" {  } { { "db/mux_ldc.tdf" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/数据装入器/db/mux_ldc.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mux:Mux1 " "Info: Elaborated megafunction instantiation \"lpm_mux:Mux1\"" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/数据装入器/loader.vhd" 21 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mux:Mux3 " "Info: Elaborated megafunction instantiation \"lpm_mux:Mux3\"" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/数据装入器/loader.vhd" 21 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mux:Mux15 " "Info: Elaborated megafunction instantiation \"lpm_mux:Mux15\"" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/数据装入器/loader.vhd" 21 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Functional Simulation Netlist Generation 0 s 1  Quartus II " "Info: Quartus II Functional Simulation Netlist Generation was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "135 " "Info: Allocated 135 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 26 21:25:41 2007 " "Info: Processing ended: Wed Sep 26 21:25:41 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Info: Elapsed time: 00:00:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}