📄 loader.map.rpt
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; -- arithmetic mode ; 0 ;
; -- qfbk mode ; 0 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 0 ;
; -- asynchronous clear/load mode ; 0 ;
; ; ;
; Total registers ; 0 ;
; I/O pins ; 0 ;
; Maximum fan-out node ; load_clk ;
; Maximum fan-out ; 18 ;
; Total fan-out ; 109 ;
; Average fan-out ; 1.56 ;
+---------------------------------------------+----------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |loader ; 34 (34) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 34 (34) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |loader ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+----------------------------------------------------------------------------------------------------+
; User-Specified and Inferred Latches ;
+-----------------------------------------------------+---------------------+------------------------+
; Latch Name ; Latch Enable Signal ; Free of Timing Hazards ;
+-----------------------------------------------------+---------------------+------------------------+
; load_val[0]$latch ; Mux15 ; yes ;
; load_val[1]$latch ; Mux15 ; yes ;
; load_val[2]$latch ; Mux15 ; yes ;
; load_val[3]$latch ; Mux15 ; yes ;
; load_val[4]$latch ; Mux15 ; yes ;
; load_val[5]$latch ; Mux15 ; yes ;
; load_val[6]$latch ; Mux15 ; yes ;
; load_val[7]$latch ; Mux15 ; yes ;
; load_val[8]$latch ; Mux15 ; yes ;
; load_val[9]$latch ; Mux15 ; yes ;
; load_val[10]$latch ; Mux15 ; yes ;
; load_val[11]$latch ; Mux15 ; yes ;
; load_val[12]$latch ; Mux15 ; yes ;
; load_val[13]$latch ; Mux15 ; yes ;
; load_val[14]$latch ; Mux15 ; yes ;
; load_val[15]$latch ; Mux15 ; yes ;
; Number of user-specified and inferred latches = 16 ; ; ;
+-----------------------------------------------------+---------------------+------------------------+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 0 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 3:1 ; 16 bits ; 32 LEs ; 32 LEs ; 0 LEs ; No ; |loader|Mux0 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
Info: Processing started: Wed Sep 26 15:50:43 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off loader -c loader
Warning: Can't analyze file -- file D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/数据装入器/loader.vhd is missing
Warning: Using design file loader.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: loader-loader_arc
Info: Found entity 1: loader
Info: Elaborating entity "loader" for the top level hierarchy
Warning (10631): VHDL Process Statement warning at loader.vhd(14): inferring latch(es) for signal or variable "load_val", which holds its previous value in one or more paths through the process
Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for "load_val[0]"
Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for "load_val[1]"
Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for "load_val[2]"
Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for "load_val[3]"
Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for "load_val[4]"
Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for "load_val[5]"
Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for "load_val[6]"
Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for "load_val[7]"
Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for "load_val[8]"
Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for "load_val[9]"
Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for "load_val[10]"
Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for "load_val[11]"
Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for "load_val[12]"
Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for "load_val[13]"
Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for "load_val[14]"
Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for "load_val[15]"
Warning: Latch load_val[0]$latch has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal load_done
Warning: Latch load_val[1]$latch has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal load_clk
Warning: Latch load_val[2]$latch has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal load_done
Warning: Latch load_val[3]$latch has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal load_clk
Warning: Latch load_val[4]$latch has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal load_clk
Warning: Latch load_val[5]$latch has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal load_clk
Warning: Latch load_val[6]$latch has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal load_done
Warning: Latch load_val[7]$latch has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal load_clk
Warning: Latch load_val[8]$latch has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal load_done
Warning: Latch load_val[9]$latch has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal load_done
Warning: Latch load_val[10]$latch has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal load_clk
Warning: Latch load_val[11]$latch has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal load_clk
Warning: Latch load_val[12]$latch has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal load_clk
Warning: Latch load_val[13]$latch has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal load_done
Warning: Latch load_val[14]$latch has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal load_clk
Warning: Latch load_val[15]$latch has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal load_clk
Info: Implemented 70 device resources after synthesis - the final resource count might be different
Info: Implemented 19 input pins
Info: Implemented 17 output pins
Info: Implemented 34 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 35 warnings
Info: Allocated 130 megabytes of memory during processing
Info: Processing ended: Wed Sep 26 15:50:48 2007
Info: Elapsed time: 00:00:05
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