state_control.map.rpt

该芯片的功能是： ① 有一复位开关

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                               ;
+----------------------------------+-----------------+-----------------+-----------------------------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path                                                                  ;
+----------------------------------+-----------------+-----------------+-----------------------------------------------------------------------------------------------+
; state_control.vhd                ; yes             ; User VHDL File  ; D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/控制状态机模块/state_control.vhd ;
+----------------------------------+-----------------+-----------------+-----------------------------------------------------------------------------------------------+


+------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                      ;
+---------------------------------------------+--------------------+
; Resource                                    ; Usage              ;
+---------------------------------------------+--------------------+
; Total logic elements                        ; 11                 ;
;     -- Combinational with no register       ; 6                  ;
;     -- Register only                        ; 1                  ;
;     -- Combinational with a register        ; 4                  ;
;                                             ;                    ;
; Logic element usage by number of LUT inputs ;                    ;
;     -- 4 input functions                    ; 3                  ;
;     -- 3 input functions                    ; 5                  ;
;     -- 2 input functions                    ; 2                  ;
;     -- 1 input functions                    ; 0                  ;
;     -- 0 input functions                    ; 0                  ;
;                                             ;                    ;
; Logic elements by mode                      ;                    ;
;     -- normal mode                          ; 11                 ;
;     -- arithmetic mode                      ; 0                  ;
;     -- qfbk mode                            ; 0                  ;
;     -- register cascade mode                ; 0                  ;
;     -- synchronous clear/load mode          ; 0                  ;
;     -- asynchronous clear/load mode         ; 5                  ;
;                                             ;                    ;
; Total registers                             ; 5                  ;
; I/O pins                                    ; 0                  ;
; Maximum fan-out node                        ; current_state.idle ;
; Maximum fan-out                             ; 6                  ;
; Total fan-out                               ; 46                 ;
; Average fan-out                             ; 2.19               ;
+---------------------------------------------+--------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                     ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |state_control             ; 11 (11)     ; 5            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 6 (6)        ; 1 (1)             ; 4 (4)            ; 0 (0)           ; 0 (0)      ; |state_control      ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


Encoding Type:  One-Hot
+-------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |state_control|current_state                                                                                                    ;
+-------------------------+------------------------+---------------------+-------------------------+-------------------------+--------------------+
; Name                    ; current_state.done_msg ; current_state.timer ; current_state.set_clock ; current_state.lamp_test ; current_state.idle ;
+-------------------------+------------------------+---------------------+-------------------------+-------------------------+--------------------+
; current_state.idle      ; 0                      ; 0                   ; 0                       ; 0                       ; 0                  ;
; current_state.lamp_test ; 0                      ; 0                   ; 0                       ; 1                       ; 1                  ;
; current_state.set_clock ; 0                      ; 0                   ; 1                       ; 0                       ; 1                  ;
; current_state.timer     ; 0                      ; 1                   ; 0                       ; 0                       ; 1                  ;
; current_state.done_msg  ; 1                      ; 0                   ; 0                       ; 0                       ; 1                  ;
+-------------------------+------------------------+---------------------+-------------------------+-------------------------+--------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 5     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 5     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Wed Sep 26 20:27:07 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off state_control -c state_control
Info: Found 3 design units, including 1 entities, in source file state_control.vhd
    Info: Found design unit 1: state_pack
    Info: Found design unit 2: state_control-state_control_arc
    Info: Found entity 1: state_control
Info: Elaborating entity "state_control" for the top level hierarchy
Info: State machine "|state_control|current_state" contains 5 states
Info: Selected Auto state machine encoding method for state machine "|state_control|current_state"
Info: Encoding result for state machine "|state_control|current_state"
    Info: Completed encoding using 5 state bits
        Info: Encoded state bit "current_state.done_msg"
        Info: Encoded state bit "current_state.timer"
        Info: Encoded state bit "current_state.set_clock"
        Info: Encoded state bit "current_state.lamp_test"
        Info: Encoded state bit "current_state.idle"
    Info: State "|state_control|current_state.idle" uses code string "00000"
    Info: State "|state_control|current_state.lamp_test" uses code string "00011"
    Info: State "|state_control|current_state.set_clock" uses code string "00101"
    Info: State "|state_control|current_state.timer" uses code string "01001"
    Info: State "|state_control|current_state.done_msg" uses code string "10001"
Info: Implemented 21 device resources after synthesis - the final resource count might be different
    Info: Implemented 6 input pins
    Info: Implemented 4 output pins
    Info: Implemented 11 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Allocated 139 megabytes of memory during processing
    Info: Processing ended: Wed Sep 26 20:27:10 2007
    Info: Elapsed time: 00:00:03