state_control.tan.qmsg

该芯片的功能是： ① 有一复位开关

{ "Info" "ITDB_TH_RESULT" "current_state.done_msg done clk -2.037 ns register " "Info: th for register \"current_state.done_msg\" (data pin = \"done\", clock pin = \"clk\") is -2.037 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.890 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.890 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 5 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 5; CLK Node = 'clk'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "state_control.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/控制状态机模块/state_control.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.520 ns) + CELL(0.542 ns) 2.890 ns current_state.done_msg 2 REG LC_X33_Y30_N5 1 " "Info: 2: + IC(1.520 ns) + CELL(0.542 ns) = 2.890 ns; Loc. = LC_X33_Y30_N5; Fanout = 1; REG Node = 'current_state.done_msg'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.062 ns" { clk current_state.done_msg } "NODE_NAME" } } { "state_control.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/控制状态机模块/state_control.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 47.40 % ) " "Info: Total cell delay = 1.370 ns ( 47.40 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.520 ns ( 52.60 % ) " "Info: Total interconnect delay = 1.520 ns ( 52.60 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.890 ns" { clk current_state.done_msg } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "2.890 ns" { clk clk~out0 current_state.done_msg } { 0.000ns 0.000ns 1.520ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" {  } { { "state_control.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/控制状态机模块/state_control.vhd" 22 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.027 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.027 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns done 1 PIN PIN_J9 5 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_J9; Fanout = 5; PIN Node = 'done'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { done } "NODE_NAME" } } { "state_control.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/控制状态机模块/state_control.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.717 ns) + CELL(0.223 ns) 5.027 ns current_state.done_msg 2 REG LC_X33_Y30_N5 1 " "Info: 2: + IC(3.717 ns) + CELL(0.223 ns) = 5.027 ns; Loc. = LC_X33_Y30_N5; Fanout = 1; REG Node = 'current_state.done_msg'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.940 ns" { done current_state.done_msg } "NODE_NAME" } } { "state_control.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/控制状态机模块/state_control.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.310 ns ( 26.06 % ) " "Info: Total cell delay = 1.310 ns ( 26.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.717 ns ( 73.94 % ) " "Info: Total interconnect delay = 3.717 ns ( 73.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.027 ns" { done current_state.done_msg } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "5.027 ns" { done done~out0 current_state.done_msg } { 0.000ns 0.000ns 3.717ns } { 0.000ns 1.087ns 0.223ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.890 ns" { clk current_state.done_msg } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "2.890 ns" { clk clk~out0 current_state.done_msg } { 0.000ns 0.000ns 1.520ns } { 0.000ns 0.828ns 0.542ns } "" } } { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.027 ns" { done current_state.done_msg } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "5.027 ns" { done done~out0 current_state.done_msg } { 0.000ns 0.000ns 3.717ns } { 0.000ns 1.087ns 0.223ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "100 " "Info: Allocated 100 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 26 20:27:37 2007 " "Info: Processing ended: Wed Sep 26 20:27:37 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}