📄 state_control.tan.qmsg
字号:
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register current_state.idle current_state.timer 422.12 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 422.12 MHz between source register \"current_state.idle\" and destination register \"current_state.timer\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.369 ns " "Info: fmax restricted to clock pin edge rate 2.369 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.879 ns + Longest register register " "Info: + Longest register to register delay is 0.879 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns current_state.idle 1 REG LC_X33_Y30_N4 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X33_Y30_N4; Fanout = 6; REG Node = 'current_state.idle'" { } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { current_state.idle } "NODE_NAME" } } { "state_control.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/控制状态机模块/state_control.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.447 ns) + CELL(0.075 ns) 0.522 ns Selector5~30 2 COMB LC_X33_Y30_N2 2 " "Info: 2: + IC(0.447 ns) + CELL(0.075 ns) = 0.522 ns; Loc. = LC_X33_Y30_N2; Fanout = 2; COMB Node = 'Selector5~30'" { } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.522 ns" { current_state.idle Selector5~30 } "NODE_NAME" } } { "state_control.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/控制状态机模块/state_control.vhd" 40 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.134 ns) + CELL(0.223 ns) 0.879 ns current_state.timer 3 REG LC_X33_Y30_N3 5 " "Info: 3: + IC(0.134 ns) + CELL(0.223 ns) = 0.879 ns; Loc. = LC_X33_Y30_N3; Fanout = 5; REG Node = 'current_state.timer'" { } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.357 ns" { Selector5~30 current_state.timer } "NODE_NAME" } } { "state_control.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/控制状态机模块/state_control.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.298 ns ( 33.90 % ) " "Info: Total cell delay = 0.298 ns ( 33.90 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.581 ns ( 66.10 % ) " "Info: Total interconnect delay = 0.581 ns ( 66.10 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.879 ns" { current_state.idle Selector5~30 current_state.timer } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "0.879 ns" { current_state.idle Selector5~30 current_state.timer } { 0.000ns 0.447ns 0.134ns } { 0.000ns 0.075ns 0.223ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.890 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.890 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 5 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 5; CLK Node = 'clk'" { } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "state_control.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/控制状态机模块/state_control.vhd" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.520 ns) + CELL(0.542 ns) 2.890 ns current_state.timer 2 REG LC_X33_Y30_N3 5 " "Info: 2: + IC(1.520 ns) + CELL(0.542 ns) = 2.890 ns; Loc. = LC_X33_Y30_N3; Fanout = 5; REG Node = 'current_state.timer'" { } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.062 ns" { clk current_state.timer } "NODE_NAME" } } { "state_control.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/控制状态机模块/state_control.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 47.40 % ) " "Info: Total cell delay = 1.370 ns ( 47.40 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.520 ns ( 52.60 % ) " "Info: Total interconnect delay = 1.520 ns ( 52.60 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.890 ns" { clk current_state.timer } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "2.890 ns" { clk clk~out0 current_state.timer } { 0.000ns 0.000ns 1.520ns } { 0.000ns 0.828ns 0.542ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.890 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.890 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 5 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 5; CLK Node = 'clk'" { } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "state_control.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/控制状态机模块/state_control.vhd" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.520 ns) + CELL(0.542 ns) 2.890 ns current_state.idle 2 REG LC_X33_Y30_N4 6 " "Info: 2: + IC(1.520 ns) + CELL(0.542 ns) = 2.890 ns; Loc. = LC_X33_Y30_N4; Fanout = 6; REG Node = 'current_state.idle'" { } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.062 ns" { clk current_state.idle } "NODE_NAME" } } { "state_control.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/控制状态机模块/state_control.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 47.40 % ) " "Info: Total cell delay = 1.370 ns ( 47.40 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.520 ns ( 52.60 % ) " "Info: Total interconnect delay = 1.520 ns ( 52.60 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.890 ns" { clk current_state.idle } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "2.890 ns" { clk clk~out0 current_state.idle } { 0.000ns 0.000ns 1.520ns } { 0.000ns 0.828ns 0.542ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.890 ns" { clk current_state.timer } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "2.890 ns" { clk clk~out0 current_state.timer } { 0.000ns 0.000ns 1.520ns } { 0.000ns 0.828ns 0.542ns } "" } } { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.890 ns" { clk current_state.idle } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "2.890 ns" { clk clk~out0 current_state.idle } { 0.000ns 0.000ns 1.520ns } { 0.000ns 0.828ns 0.542ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" { } { { "state_control.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/控制状态机模块/state_control.vhd" 22 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" { } { { "state_control.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/控制状态机模块/state_control.vhd" 22 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.879 ns" { current_state.idle Selector5~30 current_state.timer } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "0.879 ns" { current_state.idle Selector5~30 current_state.timer } { 0.000ns 0.447ns 0.134ns } { 0.000ns 0.075ns 0.223ns } "" } } { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.890 ns" { clk current_state.timer } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "2.890 ns" { clk clk~out0 current_state.timer } { 0.000ns 0.000ns 1.520ns } { 0.000ns 0.828ns 0.542ns } "" } } { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.890 ns" { clk current_state.idle } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "2.890 ns" { clk clk~out0 current_state.idle } { 0.000ns 0.000ns 1.520ns } { 0.000ns 0.828ns 0.542ns } "" } } } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0} } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { current_state.timer } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { current_state.timer } { } { } "" } } { "state_control.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/控制状态机模块/state_control.vhd" 22 -1 0 } } } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "current_state.idle done clk 3.066 ns register " "Info: tsu for register \"current_state.idle\" (data pin = \"done\", clock pin = \"clk\") is 3.066 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.946 ns + Longest pin register " "Info: + Longest pin to register delay is 5.946 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns done 1 PIN PIN_J9 5 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_J9; Fanout = 5; PIN Node = 'done'" { } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { done } "NODE_NAME" } } { "state_control.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/控制状态机模块/state_control.vhd" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.730 ns) + CELL(0.366 ns) 5.183 ns Selector3~68 2 COMB LC_X33_Y30_N9 1 " "Info: 2: + IC(3.730 ns) + CELL(0.366 ns) = 5.183 ns; Loc. = LC_X33_Y30_N9; Fanout = 1; COMB Node = 'Selector3~68'" { } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.096 ns" { done Selector3~68 } "NODE_NAME" } } { "state_control.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/控制状态机模块/state_control.vhd" 40 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.458 ns) 5.946 ns current_state.idle 3 REG LC_X33_Y30_N4 6 " "Info: 3: + IC(0.305 ns) + CELL(0.458 ns) = 5.946 ns; Loc. = LC_X33_Y30_N4; Fanout = 6; REG Node = 'current_state.idle'" { } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.763 ns" { Selector3~68 current_state.idle } "NODE_NAME" } } { "state_control.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/控制状态机模块/state_control.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.911 ns ( 32.14 % ) " "Info: Total cell delay = 1.911 ns ( 32.14 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.035 ns ( 67.86 % ) " "Info: Total interconnect delay = 4.035 ns ( 67.86 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.946 ns" { done Selector3~68 current_state.idle } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "5.946 ns" { done done~out0 Selector3~68 current_state.idle } { 0.000ns 0.000ns 3.730ns 0.305ns } { 0.000ns 1.087ns 0.366ns 0.458ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" { } { { "state_control.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/控制状态机模块/state_control.vhd" 22 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.890 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.890 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 5 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 5; CLK Node = 'clk'" { } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "state_control.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/控制状态机模块/state_control.vhd" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.520 ns) + CELL(0.542 ns) 2.890 ns current_state.idle 2 REG LC_X33_Y30_N4 6 " "Info: 2: + IC(1.520 ns) + CELL(0.542 ns) = 2.890 ns; Loc. = LC_X33_Y30_N4; Fanout = 6; REG Node = 'current_state.idle'" { } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.062 ns" { clk current_state.idle } "NODE_NAME" } } { "state_control.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/控制状态机模块/state_control.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 47.40 % ) " "Info: Total cell delay = 1.370 ns ( 47.40 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.520 ns ( 52.60 % ) " "Info: Total interconnect delay = 1.520 ns ( 52.60 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.890 ns" { clk current_state.idle } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "2.890 ns" { clk clk~out0 current_state.idle } { 0.000ns 0.000ns 1.520ns } { 0.000ns 0.828ns 0.542ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.946 ns" { done Selector3~68 current_state.idle } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "5.946 ns" { done done~out0 Selector3~68 current_state.idle } { 0.000ns 0.000ns 3.730ns 0.305ns } { 0.000ns 1.087ns 0.366ns 0.458ns } "" } } { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.890 ns" { clk current_state.idle } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "2.890 ns" { clk clk~out0 current_state.idle } { 0.000ns 0.000ns 1.520ns } { 0.000ns 0.828ns 0.542ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk load_clk current_state.idle 7.396 ns register " "Info: tco from clock \"clk\" to destination pin \"load_clk\" through register \"current_state.idle\" is 7.396 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.890 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.890 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 5 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 5; CLK Node = 'clk'" { } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "state_control.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/控制状态机模块/state_control.vhd" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.520 ns) + CELL(0.542 ns) 2.890 ns current_state.idle 2 REG LC_X33_Y30_N4 6 " "Info: 2: + IC(1.520 ns) + CELL(0.542 ns) = 2.890 ns; Loc. = LC_X33_Y30_N4; Fanout = 6; REG Node = 'current_state.idle'" { } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.062 ns" { clk current_state.idle } "NODE_NAME" } } { "state_control.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/控制状态机模块/state_control.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 47.40 % ) " "Info: Total cell delay = 1.370 ns ( 47.40 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.520 ns ( 52.60 % ) " "Info: Total interconnect delay = 1.520 ns ( 52.60 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.890 ns" { clk current_state.idle } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "2.890 ns" { clk clk~out0 current_state.idle } { 0.000ns 0.000ns 1.520ns } { 0.000ns 0.828ns 0.542ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" { } { { "state_control.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/控制状态机模块/state_control.vhd" 22 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.350 ns + Longest register pin " "Info: + Longest register to pin delay is 4.350 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns current_state.idle 1 REG LC_X33_Y30_N4 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X33_Y30_N4; Fanout = 6; REG Node = 'current_state.idle'" { } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { current_state.idle } "NODE_NAME" } } { "state_control.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/控制状态机模块/state_control.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.459 ns) + CELL(0.366 ns) 0.825 ns Selector1~22 2 COMB LC_X33_Y30_N8 1 " "Info: 2: + IC(0.459 ns) + CELL(0.366 ns) = 0.825 ns; Loc. = LC_X33_Y30_N8; Fanout = 1; COMB Node = 'Selector1~22'" { } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.825 ns" { current_state.idle Selector1~22 } "NODE_NAME" } } { "state_control.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/控制状态机模块/state_control.vhd" 40 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.121 ns) + CELL(2.404 ns) 4.350 ns load_clk 3 PIN PIN_H10 0 " "Info: 3: + IC(1.121 ns) + CELL(2.404 ns) = 4.350 ns; Loc. = PIN_H10; Fanout = 0; PIN Node = 'load_clk'" { } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.525 ns" { Selector1~22 load_clk } "NODE_NAME" } } { "state_control.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/控制状态机模块/state_control.vhd" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.770 ns ( 63.68 % ) " "Info: Total cell delay = 2.770 ns ( 63.68 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.580 ns ( 36.32 % ) " "Info: Total interconnect delay = 1.580 ns ( 36.32 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.350 ns" { current_state.idle Selector1~22 load_clk } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "4.350 ns" { current_state.idle Selector1~22 load_clk } { 0.000ns 0.459ns 1.121ns } { 0.000ns 0.366ns 2.404ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.890 ns" { clk current_state.idle } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "2.890 ns" { clk clk~out0 current_state.idle } { 0.000ns 0.000ns 1.520ns } { 0.000ns 0.828ns 0.542ns } "" } } { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.350 ns" { current_state.idle Selector1~22 load_clk } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "4.350 ns" { current_state.idle Selector1~22 load_clk } { 0.000ns 0.459ns 1.121ns } { 0.000ns 0.366ns 2.404ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "test cook 9.086 ns Longest " "Info: Longest tpd from source pin \"test\" to destination pin \"cook\" is 9.086 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns test 1 PIN PIN_B8 6 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_B8; Fanout = 6; PIN Node = 'test'" { } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { test } "NODE_NAME" } } { "state_control.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/控制状态机模块/state_control.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.900 ns) + CELL(0.366 ns) 5.353 ns Selector5~30 2 COMB LC_X33_Y30_N2 2 " "Info: 2: + IC(3.900 ns) + CELL(0.366 ns) = 5.353 ns; Loc. = LC_X33_Y30_N2; Fanout = 2; COMB Node = 'Selector5~30'" { } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.266 ns" { test Selector5~30 } "NODE_NAME" } } { "state_control.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/控制状态机模块/state_control.vhd" 40 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.134 ns) + CELL(0.075 ns) 5.562 ns Selector5~31 3 COMB LC_X33_Y30_N3 1 " "Info: 3: + IC(0.134 ns) + CELL(0.075 ns) = 5.562 ns; Loc. = LC_X33_Y30_N3; Fanout = 1; COMB Node = 'Selector5~31'" { } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.209 ns" { Selector5~30 Selector5~31 } "NODE_NAME" } } { "state_control.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/控制状态机模块/state_control.vhd" 40 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.120 ns) + CELL(2.404 ns) 9.086 ns cook 4 PIN PIN_F10 0 " "Info: 4: + IC(1.120 ns) + CELL(2.404 ns) = 9.086 ns; Loc. = PIN_F10; Fanout = 0; PIN Node = 'cook'" { } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.524 ns" { Selector5~31 cook } "NODE_NAME" } } { "state_control.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/控制状态机模块/state_control.vhd" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.932 ns ( 43.28 % ) " "Info: Total cell delay = 3.932 ns ( 43.28 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.154 ns ( 56.72 % ) " "Info: Total interconnect delay = 5.154 ns ( 56.72 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "9.086 ns" { test Selector5~30 Selector5~31 cook } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "9.086 ns" { test test~out0 Selector5~30 Selector5~31 cook } { 0.000ns 0.000ns 3.900ns 0.134ns 1.120ns } { 0.000ns 1.087ns 0.366ns 0.075ns 2.404ns } "" } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
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