state_control.tan.rpt

该芯片的功能是： ① 有一复位开关

; N/A   ; None         ; 7.392 ns   ; current_state.lamp_test ; load_8888 ; clk        ;
; N/A   ; None         ; 7.322 ns   ; current_state.idle      ; load_8888 ; clk        ;
; N/A   ; None         ; 7.301 ns   ; current_state.idle      ; cook      ; clk        ;
; N/A   ; None         ; 7.227 ns   ; current_state.done_msg  ; load_done ; clk        ;
; N/A   ; None         ; 7.170 ns   ; current_state.timer     ; load_done ; clk        ;
; N/A   ; None         ; 7.037 ns   ; current_state.set_clock ; load_clk  ; clk        ;
; N/A   ; None         ; 6.800 ns   ; current_state.timer     ; cook      ; clk        ;
+-------+--------------+------------+-------------------------+-----------+------------+


+----------------------------------------------------------------------+
; tpd                                                                  ;
+-------+-------------------+-----------------+------------+-----------+
; Slack ; Required P2P Time ; Actual P2P Time ; From       ; To        ;
+-------+-------------------+-----------------+------------+-----------+
; N/A   ; None              ; 9.086 ns        ; test       ; cook      ;
; N/A   ; None              ; 9.003 ns        ; test       ; load_8888 ;
; N/A   ; None              ; 8.833 ns        ; start_cook ; cook      ;
; N/A   ; None              ; 8.805 ns        ; set_time   ; cook      ;
; N/A   ; None              ; 8.705 ns        ; done       ; cook      ;
; N/A   ; None              ; 8.693 ns        ; test       ; load_clk  ;
; N/A   ; None              ; 8.603 ns        ; set_time   ; load_clk  ;
; N/A   ; None              ; 8.401 ns        ; done       ; load_done ;
+-------+-------------------+-----------------+------------+-----------+


+-------------------------------------------------------------------------------------------+
; th                                                                                        ;
+---------------+-------------+-----------+------------+-------------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From       ; To                      ; To Clock ;
+---------------+-------------+-----------+------------+-------------------------+----------+
; N/A           ; None        ; -2.037 ns ; done       ; current_state.done_msg  ; clk      ;
; N/A           ; None        ; -2.262 ns ; set_time   ; current_state.set_clock ; clk      ;
; N/A           ; None        ; -2.317 ns ; test       ; current_state.set_clock ; clk      ;
; N/A           ; None        ; -2.364 ns ; done       ; current_state.timer     ; clk      ;
; N/A           ; None        ; -2.439 ns ; set_time   ; current_state.timer     ; clk      ;
; N/A           ; None        ; -2.441 ns ; test       ; current_state.lamp_test ; clk      ;
; N/A           ; None        ; -2.467 ns ; start_cook ; current_state.timer     ; clk      ;
; N/A           ; None        ; -2.720 ns ; test       ; current_state.timer     ; clk      ;
; N/A           ; None        ; -2.829 ns ; test       ; current_state.idle      ; clk      ;
; N/A           ; None        ; -2.850 ns ; set_time   ; current_state.idle      ; clk      ;
; N/A           ; None        ; -2.876 ns ; start_cook ; current_state.idle      ; clk      ;
; N/A           ; None        ; -2.956 ns ; done       ; current_state.idle      ; clk      ;
+---------------+-------------+-----------+------------+-------------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Wed Sep 26 20:27:36 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off state_control -c state_control --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 422.12 MHz between source register "current_state.idle" and destination register "current_state.timer"
    Info: fmax restricted to clock pin edge rate 2.369 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.879 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X33_Y30_N4; Fanout = 6; REG Node = 'current_state.idle'
            Info: 2: + IC(0.447 ns) + CELL(0.075 ns) = 0.522 ns; Loc. = LC_X33_Y30_N2; Fanout = 2; COMB Node = 'Selector5~30'
            Info: 3: + IC(0.134 ns) + CELL(0.223 ns) = 0.879 ns; Loc. = LC_X33_Y30_N3; Fanout = 5; REG Node = 'current_state.timer'
            Info: Total cell delay = 0.298 ns ( 33.90 % )
            Info: Total interconnect delay = 0.581 ns ( 66.10 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.890 ns
                Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 5; CLK Node = 'clk'
                Info: 2: + IC(1.520 ns) + CELL(0.542 ns) = 2.890 ns; Loc. = LC_X33_Y30_N3; Fanout = 5; REG Node = 'current_state.timer'
                Info: Total cell delay = 1.370 ns ( 47.40 % )
                Info: Total interconnect delay = 1.520 ns ( 52.60 % )
            Info: - Longest clock path from clock "clk" to source register is 2.890 ns
                Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 5; CLK Node = 'clk'
                Info: 2: + IC(1.520 ns) + CELL(0.542 ns) = 2.890 ns; Loc. = LC_X33_Y30_N4; Fanout = 6; REG Node = 'current_state.idle'
                Info: Total cell delay = 1.370 ns ( 47.40 % )
                Info: Total interconnect delay = 1.520 ns ( 52.60 % )
        Info: + Micro clock to output delay of source is 0.156 ns
        Info: + Micro setup delay of destination is 0.010 ns
Info: tsu for register "current_state.idle" (data pin = "done", clock pin = "clk") is 3.066 ns
    Info: + Longest pin to register delay is 5.946 ns
        Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_J9; Fanout = 5; PIN Node = 'done'
        Info: 2: + IC(3.730 ns) + CELL(0.366 ns) = 5.183 ns; Loc. = LC_X33_Y30_N9; Fanout = 1; COMB Node = 'Selector3~68'
        Info: 3: + IC(0.305 ns) + CELL(0.458 ns) = 5.946 ns; Loc. = LC_X33_Y30_N4; Fanout = 6; REG Node = 'current_state.idle'
        Info: Total cell delay = 1.911 ns ( 32.14 % )
        Info: Total interconnect delay = 4.035 ns ( 67.86 % )
    Info: + Micro setup delay of destination is 0.010 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.890 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 5; CLK Node = 'clk'
        Info: 2: + IC(1.520 ns) + CELL(0.542 ns) = 2.890 ns; Loc. = LC_X33_Y30_N4; Fanout = 6; REG Node = 'current_state.idle'
        Info: Total cell delay = 1.370 ns ( 47.40 % )
        Info: Total interconnect delay = 1.520 ns ( 52.60 % )
Info: tco from clock "clk" to destination pin "load_clk" through register "current_state.idle" is 7.396 ns
    Info: + Longest clock path from clock "clk" to source register is 2.890 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 5; CLK Node = 'clk'
        Info: 2: + IC(1.520 ns) + CELL(0.542 ns) = 2.890 ns; Loc. = LC_X33_Y30_N4; Fanout = 6; REG Node = 'current_state.idle'
        Info: Total cell delay = 1.370 ns ( 47.40 % )
        Info: Total interconnect delay = 1.520 ns ( 52.60 % )
    Info: + Micro clock to output delay of source is 0.156 ns
    Info: + Longest register to pin delay is 4.350 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X33_Y30_N4; Fanout = 6; REG Node = 'current_state.idle'
        Info: 2: + IC(0.459 ns) + CELL(0.366 ns) = 0.825 ns; Loc. = LC_X33_Y30_N8; Fanout = 1; COMB Node = 'Selector1~22'
        Info: 3: + IC(1.121 ns) + CELL(2.404 ns) = 4.350 ns; Loc. = PIN_H10; Fanout = 0; PIN Node = 'load_clk'
        Info: Total cell delay = 2.770 ns ( 63.68 % )
        Info: Total interconnect delay = 1.580 ns ( 36.32 % )
Info: Longest tpd from source pin "test" to destination pin "cook" is 9.086 ns
    Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_B8; Fanout = 6; PIN Node = 'test'
    Info: 2: + IC(3.900 ns) + CELL(0.366 ns) = 5.353 ns; Loc. = LC_X33_Y30_N2; Fanout = 2; COMB Node = 'Selector5~30'
    Info: 3: + IC(0.134 ns) + CELL(0.075 ns) = 5.562 ns; Loc. = LC_X33_Y30_N3; Fanout = 1; COMB Node = 'Selector5~31'
    Info: 4: + IC(1.120 ns) + CELL(2.404 ns) = 9.086 ns; Loc. = PIN_F10; Fanout = 0; PIN Node = 'cook'
    Info: Total cell delay = 3.932 ns ( 43.28 % )
    Info: Total interconnect delay = 5.154 ns ( 56.72 % )
Info: th for register "current_state.done_msg" (data pin = "done", clock pin = "clk") is -2.037 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.890 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 5; CLK Node = 'clk'
        Info: 2: + IC(1.520 ns) + CELL(0.542 ns) = 2.890 ns; Loc. = LC_X33_Y30_N5; Fanout = 1; REG Node = 'current_state.done_msg'
        Info: Total cell delay = 1.370 ns ( 47.40 % )
        Info: Total interconnect delay = 1.520 ns ( 52.60 % )
    Info: + Micro hold delay of destination is 0.100 ns
    Info: - Shortest pin to register delay is 5.027 ns
        Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_J9; Fanout = 5; PIN Node = 'done'
        Info: 2: + IC(3.717 ns) + CELL(0.223 ns) = 5.027 ns; Loc. = LC_X33_Y30_N5; Fanout = 1; REG Node = 'current_state.done_msg'
        Info: Total cell delay = 1.310 ns ( 26.06 % )
        Info: Total interconnect delay = 3.717 ns ( 73.94 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 100 megabytes of memory during processing
    Info: Processing ended: Wed Sep 26 20:27:37 2007
    Info: Elapsed time: 00:00:01