state_control.vhd

该芯片的功能是： ① 有一复位开关

library ieee;
use ieee.std_logic_1164.all;
package state_pack is
    type state_type is(idle,lamp_test,set_clock,timer,done_msg);
end state_pack;
library ieee;
use ieee.std_logic_1164.all;
use work.state_pack.all;
entity state_control is
    port(clk  : in std_logic;
         done : in std_logic;
         reset: in std_logic;
         test : in std_logic;
         set_time: in std_logic;
         start_cook:in std_logic;
         cook:out std_logic;
         load_8888:out std_logic;
         load_clk:out std_logic;
         load_done:out std_logic);
end state_control;
architecture state_control_arc of state_control is
    signal next_state,current_state:state_type;
begin
    process(clk,reset)
    begin
      if(reset='1') then
        current_state<=idle;
      elsif (clk'event and clk='1') then
        current_state<=next_state;
      end if;
   end process;

   process(current_state,set_time,start_cook,test,done)
   begin
      next_state<=idle;
      load_8888<='0';
      load_clk<='0';
      load_done<='0';
      cook<='0';
      case current_state is
         when lamp_test =>
              load_8888<='1';
         when set_clock =>
              load_clk<='1';
         when done_msg=>
              load_done<='1';
         when idle=>
            if(test='1') then
              next_state<=lamp_test;
              load_8888<='1';
            elsif (set_time='1')then
              next_state<=set_clock;
              load_clk<='1';
            elsif ((start_cook='1') and (done='0')) then
              next_state<=timer;
              cook<='1';
            end if;
         when timer=>
            if (done='1') then
               next_state<=done_msg;
               load_done<='1';
            else
               next_state<=timer;
               cook<='1';
            end if;
       end case;
   end process;
end state_control_arc;