📄 bcd7.vhd
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library ieee;
use ieee.std_logic_1164.all;
entity bcd7 is
port(q:in std_logic_vector(3 downto 0);
segments:out std_logic_vector(1 to 7));
end bcd7;
architecture rtl of bcd7 is
begin
process(q)
begin
case q is
when "0000"=>segments<="1111110";
when "0001"=>segments<="1100000";
when "0010"=>segments<="1011011";
when "0011"=>segments<="1110011";
when "0100"=>segments<="1100101";
when "0101"=>segments<="0110111";
when "0110"=>segments<="0111111";
when "0111"=>segments<="1100010";
when "1000"=>segments<="1111111";
when "1001"=>segments<="1110111";
when "1010"=>segments<="1111001";
when "1011"=>segments<="0111001";
when "1100"=>segments<="0101001";
when "1101"=>segments<="0011111";
when others=>segments<="0000000";
end case;
end process;
end rtl;
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