microwave_timer.fnsim.qmsg

该芯片的功能是： ① 有一复位开关

{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "load_val\[7\] loader.vhd(14) " "Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for \"load_val\[7\]\"" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/loader.vhd" 14 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "load_val\[8\] loader.vhd(14) " "Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for \"load_val\[8\]\"" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/loader.vhd" 14 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "load_val\[9\] loader.vhd(14) " "Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for \"load_val\[9\]\"" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/loader.vhd" 14 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "load_val\[10\] loader.vhd(14) " "Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for \"load_val\[10\]\"" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/loader.vhd" 14 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "load_val\[11\] loader.vhd(14) " "Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for \"load_val\[11\]\"" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/loader.vhd" 14 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "load_val\[12\] loader.vhd(14) " "Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for \"load_val\[12\]\"" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/loader.vhd" 14 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "load_val\[13\] loader.vhd(14) " "Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for \"load_val\[13\]\"" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/loader.vhd" 14 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "load_val\[14\] loader.vhd(14) " "Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for \"load_val\[14\]\"" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/loader.vhd" 14 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "load_val\[15\] loader.vhd(14) " "Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for \"load_val\[15\]\"" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/loader.vhd" 14 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "timer timer:u2 " "Info: Elaborating entity \"timer\" for hierarchy \"timer:u2\"" {  } { { "microwave_timer.vhd" "u2" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/microwave_timer.vhd" 65 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter4 timer:u2\|counter4:u3 " "Info: Elaborating entity \"counter4\" for hierarchy \"timer:u2\|counter4:u3\"" {  } { { "timer.vhd" "u3" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/timer.vhd" 56 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "zero_detect timer:u2\|counter4:u3\|zero_detect:u0 " "Info: Elaborating entity \"zero_detect\" for hierarchy \"timer:u2\|counter4:u3\|zero_detect:u0\"" {  } { { "counter4.vhd" "u0" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/counter4.vhd" 38 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bcd7 timer:u2\|counter4:u3\|bcd7:u1 " "Info: Elaborating entity \"bcd7\" for hierarchy \"timer:u2\|counter4:u3\|bcd7:u1\"" {  } { { "counter4.vhd" "u1" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/counter4.vhd" 40 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decr4 timer:u2\|counter4:u3\|decr4:u2 " "Info: Elaborating entity \"decr4\" for hierarchy \"timer:u2\|counter4:u3\|decr4:u2\"" {  } { { "counter4.vhd" "u2" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/counter4.vhd" 42 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dual_reg4 timer:u2\|counter4:u3\|dual_reg4:u3 " "Info: Elaborating entity \"dual_reg4\" for hierarchy \"timer:u2\|counter4:u3\|dual_reg4:u3\"" {  } { { "counter4.vhd" "u3" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/counter4.vhd" 44 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "d:/program files/altera/70/quartus/libraries/megafunctions/lpm_add_sub.tdf" 102 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "timer:u2\|counter4:u0\|decr4:u2\|lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"timer:u2\|counter4:u0\|decr4:u2\|lpm_add_sub:Add0\"" {  } { { "decr4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/decr4.vhd" 13 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "d:/program files/altera/70/quartus/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "timer:u2\|counter4:u0\|decr4:u2\|lpm_add_sub:Add0\|addcore:adder timer:u2\|counter4:u0\|decr4:u2\|lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"timer:u2\|counter4:u0\|decr4:u2\|lpm_add_sub:Add0\|addcore:adder\", which is child of megafunction instantiation \"timer:u2\|counter4:u0\|decr4:u2\|lpm_add_sub:Add0\"" {  } { { "lpm_add_sub.tdf" "" { Text "d:/program files/altera/70/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 4 0 } } { "decr4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/decr4.vhd" 13 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "timer:u2\|counter4:u0\|decr4:u2\|lpm_add_sub:Add0 " "Info: Instantiated megafunction \"timer:u2\|counter4:u0\|decr4:u2\|lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 5 " "Info: Parameter \"LPM_WIDTH\" = \"5\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } { { "decr4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/decr4.vhd" 13 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "a_csnbuffer.tdf" "" { Text "d:/program files/altera/70/quartus/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "timer:u2\|counter4:u0\|decr4:u2\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:oflow_node timer:u2\|counter4:u0\|decr4:u2\|lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"timer:u2\|counter4:u0\|decr4:u2\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"timer:u2\|counter4:u0\|decr4:u2\|lpm_add_sub:Add0\"" {  } { { "addcore.tdf" "" { Text "d:/program files/altera/70/quartus/libraries/megafunctions/addcore.tdf" 94 2 0 } } { "decr4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/decr4.vhd" 13 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "timer:u2\|counter4:u0\|decr4:u2\|lpm_add_sub:Add0 " "Info: Instantiated megafunction \"timer:u2\|counter4:u0\|decr4:u2\|lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 5 " "Info: Parameter \"LPM_WIDTH\" = \"5\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } { { "decr4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/decr4.vhd" 13 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}