microwave_timer.tan.qmsg

该芯片的功能是： ① 有一复位开关

{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "state_control:u0\|current_state.idle loader:u1\|load_val\[11\] clk 5.204 ns " "Info: Found hold time violation between source  pin or register \"state_control:u0\|current_state.idle\" and destination pin or register \"loader:u1\|load_val\[11\]\" for clock \"clk\" (Hold time is 5.204 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "7.201 ns + Largest " "Info: + Largest clock skew is 7.201 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 10.260 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 10.260 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 21 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 21; CLK Node = 'clk'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "microwave_timer.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/microwave_timer.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.523 ns) + CELL(0.698 ns) 3.049 ns timer:u2\|counter4:u1\|dual_reg4:u3\|q\[2\] 2 REG LC_X28_Y25_N4 10 " "Info: 2: + IC(1.523 ns) + CELL(0.698 ns) = 3.049 ns; Loc. = LC_X28_Y25_N4; Fanout = 10; REG Node = 'timer:u2\|counter4:u1\|dual_reg4:u3\|q\[2\]'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.221 ns" { clk timer:u2|counter4:u1|dual_reg4:u3|q[2] } "NODE_NAME" } } { "dual_reg4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/dual_reg4.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.401 ns) + CELL(0.366 ns) 3.816 ns timer:u2\|counter4:u1\|zero_detect:u0\|Equal0~14 3 COMB LC_X28_Y25_N5 4 " "Info: 3: + IC(0.401 ns) + CELL(0.366 ns) = 3.816 ns; Loc. = LC_X28_Y25_N5; Fanout = 4; COMB Node = 'timer:u2\|counter4:u1\|zero_detect:u0\|Equal0~14'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.767 ns" { timer:u2|counter4:u1|dual_reg4:u3|q[2] timer:u2|counter4:u1|zero_detect:u0|Equal0~14 } "NODE_NAME" } } { "zero_detect.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/zero_detect.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.788 ns) + CELL(0.280 ns) 4.884 ns state_control:u0\|Selector2~36 4 COMB LC_X24_Y25_N1 8 " "Info: 4: + IC(0.788 ns) + CELL(0.280 ns) = 4.884 ns; Loc. = LC_X24_Y25_N1; Fanout = 8; COMB Node = 'state_control:u0\|Selector2~36'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.068 ns" { timer:u2|counter4:u1|zero_detect:u0|Equal0~14 state_control:u0|Selector2~36 } "NODE_NAME" } } { "state_control.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/state_control.vhd" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.862 ns) + CELL(0.280 ns) 7.026 ns loader:u1\|Mux15~238 5 COMB LC_X1_Y17_N1 16 " "Info: 5: + IC(1.862 ns) + CELL(0.280 ns) = 7.026 ns; Loc. = LC_X1_Y17_N1; Fanout = 16; COMB Node = 'loader:u1\|Mux15~238'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.142 ns" { state_control:u0|Selector2~36 loader:u1|Mux15~238 } "NODE_NAME" } } { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/loader.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.159 ns) + CELL(0.075 ns) 10.260 ns loader:u1\|load_val\[11\] 6 REG LC_X1_Y17_N2 1 " "Info: 6: + IC(3.159 ns) + CELL(0.075 ns) = 10.260 ns; Loc. = LC_X1_Y17_N2; Fanout = 1; REG Node = 'loader:u1\|load_val\[11\]'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.234 ns" { loader:u1|Mux15~238 loader:u1|load_val[11] } "NODE_NAME" } } { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/loader.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.527 ns ( 24.63 % ) " "Info: Total cell delay = 2.527 ns ( 24.63 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.733 ns ( 75.37 % ) " "Info: Total interconnect delay = 7.733 ns ( 75.37 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "10.260 ns" { clk timer:u2|counter4:u1|dual_reg4:u3|q[2] timer:u2|counter4:u1|zero_detect:u0|Equal0~14 state_control:u0|Selector2~36 loader:u1|Mux15~238 loader:u1|load_val[11] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "10.260 ns" { clk clk~out0 timer:u2|counter4:u1|dual_reg4:u3|q[2] timer:u2|counter4:u1|zero_detect:u0|Equal0~14 state_control:u0|Selector2~36 loader:u1|Mux15~238 loader:u1|load_val[11] } { 0.000ns 0.000ns 1.523ns 0.401ns 0.788ns 1.862ns 3.159ns } { 0.000ns 0.828ns 0.698ns 0.366ns 0.280ns 0.280ns 0.075ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.059 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 3.059 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 21 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 21; CLK Node = 'clk'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "microwave_timer.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/microwave_timer.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.689 ns) + CELL(0.542 ns) 3.059 ns state_control:u0\|current_state.idle 2 REG LC_X1_Y17_N4 6 " "Info: 2: + IC(1.689 ns) + CELL(0.542 ns) = 3.059 ns; Loc. = LC_X1_Y17_N4; Fanout = 6; REG Node = 'state_control:u0\|current_state.idle'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.231 ns" { clk state_control:u0|current_state.idle } "NODE_NAME" } } { "state_control.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/state_control.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 44.79 % ) " "Info: Total cell delay = 1.370 ns ( 44.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.689 ns ( 55.21 % ) " "Info: Total interconnect delay = 1.689 ns ( 55.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.059 ns" { clk state_control:u0|current_state.idle } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "3.059 ns" { clk clk~out0 state_control:u0|current_state.idle } { 0.000ns 0.000ns 1.689ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "10.260 ns" { clk timer:u2|counter4:u1|dual_reg4:u3|q[2] timer:u2|counter4:u1|zero_detect:u0|Equal0~14 state_control:u0|Selector2~36 loader:u1|Mux15~238 loader:u1|load_val[11] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "10.260 ns" { clk clk~out0 timer:u2|counter4:u1|dual_reg4:u3|q[2] timer:u2|counter4:u1|zero_detect:u0|Equal0~14 state_control:u0|Selector2~36 loader:u1|Mux15~238 loader:u1|load_val[11] } { 0.000ns 0.000ns 1.523ns 0.401ns 0.788ns 1.862ns 3.159ns } { 0.000ns 0.828ns 0.698ns 0.366ns 0.280ns 0.280ns 0.075ns } "" } } { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.059 ns" { clk state_control:u0|current_state.idle } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "3.059 ns" { clk clk~out0 state_control:u0|current_state.idle } { 0.000ns 0.000ns 1.689ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns - " "Info: - Micro clock to output delay of source is 0.156 ns" {  } { { "state_control.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/state_control.vhd" 22 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.841 ns - Shortest register register " "Info: - Shortest register to register delay is 1.841 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns state_control:u0\|current_state.idle 1 REG LC_X1_Y17_N4 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y17_N4; Fanout = 6; REG Node = 'state_control:u0\|current_state.idle'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { state_control:u0|current_state.idle } "NODE_NAME" } } { "state_control.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/state_control.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.405 ns) + CELL(0.075 ns) 0.480 ns state_control:u0\|Selector1~63 2 COMB LC_X1_Y17_N3 18 " "Info: 2: + IC(0.405 ns) + CELL(0.075 ns) = 0.480 ns; Loc. = LC_X1_Y17_N3; Fanout = 18; COMB Node = 'state_control:u0\|Selector1~63'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.480 ns" { state_control:u0|current_state.idle state_control:u0|Selector1~63 } "NODE_NAME" } } { "state_control.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/state_control.vhd" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.496 ns) + CELL(0.183 ns) 1.159 ns loader:u1\|Mux11~32 3 COMB LC_X1_Y17_N6 1 " "Info: 3: + IC(0.496 ns) + CELL(0.183 ns) = 1.159 ns; Loc. = LC_X1_Y17_N6; Fanout = 1; COMB Node = 'loader:u1\|Mux11~32'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.679 ns" { state_control:u0|Selector1~63 loader:u1|Mux11~32 } "NODE_NAME" } } { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/loader.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.499 ns) + CELL(0.183 ns) 1.841 ns loader:u1\|load_val\[11\] 4 REG LC_X1_Y17_N2 1 " "Info: 4: + IC(0.499 ns) + CELL(0.183 ns) = 1.841 ns; Loc. = LC_X1_Y17_N2; Fanout = 1; REG Node = 'loader:u1\|load_val\[11\]'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.682 ns" { loader:u1|Mux11~32 loader:u1|load_val[11] } "NODE_NAME" } } { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/loader.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.441 ns ( 23.95 % ) " "Info: Total cell delay = 0.441 ns ( 23.95 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns ( 76.05 % ) " "Info: Total interconnect delay = 1.400 ns ( 76.05 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.841 ns" { state_control:u0|current_state.idle state_control:u0|Selector1~63 loader:u1|Mux11~32 loader:u1|load_val[11] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "1.841 ns" { state_control:u0|current_state.idle state_control:u0|Selector1~63 loader:u1|Mux11~32 loader:u1|load_val[11] } { 0.000ns 0.405ns 0.496ns 0.499ns } { 0.000ns 0.075ns 0.183ns 0.183ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/loader.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "state_control.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/state_control.vhd" 22 -1 0 } } { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/loader.vhd" 14 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "10.260 ns" { clk timer:u2|counter4:u1|dual_reg4:u3|q[2] timer:u2|counter4:u1|zero_detect:u0|Equal0~14 state_control:u0|Selector2~36 loader:u1|Mux15~238 loader:u1|load_val[11] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "10.260 ns" { clk clk~out0 timer:u2|counter4:u1|dual_reg4:u3|q[2] timer:u2|counter4:u1|zero_detect:u0|Equal0~14 state_control:u0|Selector2~36 loader:u1|Mux15~238 loader:u1|load_val[11] } { 0.000ns 0.000ns 1.523ns 0.401ns 0.788ns 1.862ns 3.159ns } { 0.000ns 0.828ns 0.698ns 0.366ns 0.280ns 0.280ns 0.075ns } "" } } { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.059 ns" { clk state_control:u0|current_state.idle } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "3.059 ns" { clk clk~out0 state_control:u0|current_state.idle } { 0.000ns 0.000ns 1.689ns } { 0.000ns 0.828ns 0.542ns } "" } } { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.841 ns" { state_control:u0|current_state.idle state_control:u0|Selector1~63 loader:u1|Mux11~32 loader:u1|load_val[11] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "1.841 ns" { state_control:u0|current_state.idle state_control:u0|Selector1~63 loader:u1|Mux11~32 loader:u1|load_val[11] } { 0.000ns 0.405ns 0.496ns 0.499ns } { 0.000ns 0.075ns 0.183ns 0.183ns } "" } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "timer:u2\|counter4:u0\|dual_reg4:u3\|q\[2\] set_time clk 6.605 ns register " "Info: tsu for register \"timer:u2\|counter4:u0\|dual_reg4:u3\|q\[2\]\" (data pin = \"set_time\", clock pin = \"clk\") is 6.605 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.516 ns + Longest pin register " "Info: + Longest pin to register delay is 9.516 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns set_time 1 CLK PIN_Y21 4 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_Y21; Fanout = 4; CLK Node = 'set_time'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { set_time } "NODE_NAME" } } { "microwave_timer.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/microwave_timer.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.493 ns) + CELL(0.075 ns) 5.655 ns state_control:u0\|Selector5~41 2 COMB LC_X1_Y17_N0 3 " "Info: 2: + IC(4.493 ns) + CELL(0.075 ns) = 5.655 ns; Loc. = LC_X1_Y17_N0; Fanout = 3; COMB Node = 'state_control:u0\|Selector5~41'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.568 ns" { set_time state_control:u0|Selector5~41 } "NODE_NAME" } } { "state_control.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/state_control.vhd" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.040 ns) + CELL(0.366 ns) 8.061 ns timer:u2\|counter4:u0\|dual_reg4:u3\|q\[0\]~349 3 COMB LC_X21_Y25_N2 4 " "Info: 3: + IC(2.040 ns) + CELL(0.366 ns) = 8.061 ns; Loc. = LC_X21_Y25_N2; Fanout = 4; COMB Node = 'timer:u2\|counter4:u0\|dual_reg4:u3\|q\[0\]~349'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.406 ns" { state_control:u0|Selector5~41 timer:u2|counter4:u0|dual_reg4:u3|q[0]~349 } "NODE_NAME" } } { "dual_reg4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/dual_reg4.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.750 ns) + CELL(0.705 ns) 9.516 ns timer:u2\|counter4:u0\|dual_reg4:u3\|q\[2\] 4 REG LC_X23_Y25_N7 9 " "Info: 4: + IC(0.750 ns) + CELL(0.705 ns) = 9.516 ns; Loc. = LC_X23_Y25_N7; Fanout = 9; REG Node = 'timer:u2\|counter4:u0\|dual_reg4:u3\|q\[2\]'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.455 ns" { timer:u2|counter4:u0|dual_reg4:u3|q[0]~349 timer:u2|counter4:u0|dual_reg4:u3|q[2] } "NODE_NAME" } } { "dual_reg4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/dual_reg4.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.233 ns ( 23.47 % ) " "Info: Total cell delay = 2.233 ns ( 23.47 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.283 ns ( 76.53 % ) " "Info: Total interconnect delay = 7.283 ns ( 76.53 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "9.516 ns" { set_time state_control:u0|Selector5~41 timer:u2|counter4:u0|dual_reg4:u3|q[0]~349 timer:u2|counter4:u0|dual_reg4:u3|q[2] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "9.516 ns" { set_time set_time~out0 state_control:u0|Selector5~41 timer:u2|counter4:u0|dual_reg4:u3|q[0]~349 timer:u2|counter4:u0|dual_reg4:u3|q[2] } { 0.000ns 0.000ns 4.493ns 2.040ns 0.750ns } { 0.000ns 1.087ns 0.075ns 0.366ns 0.705ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "dual_reg4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/dual_reg4.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.921 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.921 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 21 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 21; CLK Node = 'clk'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "microwave_timer.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/microwave_timer.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.551 ns) + CELL(0.542 ns) 2.921 ns timer:u2\|counter4:u0\|dual_reg4:u3\|q\[2\] 2 REG LC_X23_Y25_N7 9 " "Info: 2: + IC(1.551 ns) + CELL(0.542 ns) = 2.921 ns; Loc. = LC_X23_Y25_N7; Fanout = 9; REG Node = 'timer:u2\|counter4:u0\|dual_reg4:u3\|q\[2\]'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.093 ns" { clk timer:u2|counter4:u0|dual_reg4:u3|q[2] } "NODE_NAME" } } { "dual_reg4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/dual_reg4.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 46.90 % ) " "Info: Total cell delay = 1.370 ns ( 46.90 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.551 ns ( 53.10 % ) " "Info: Total interconnect delay = 1.551 ns ( 53.10 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.921 ns" { clk timer:u2|counter4:u0|dual_reg4:u3|q[2] } "N