microwave_timer.tan.qmsg

该芯片的功能是： ① 有一复位开关

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register loader:u1\|load_val\[11\] register timer:u2\|counter4:u2\|dual_reg4:u3\|q\[3\] 52.23 MHz 19.146 ns Internal " "Info: Clock \"clk\" has Internal fmax of 52.23 MHz between source register \"loader:u1\|load_val\[11\]\" and destination register \"timer:u2\|counter4:u2\|dual_reg4:u3\|q\[3\]\" (period= 19.146 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.224 ns + Longest register register " "Info: + Longest register to register delay is 2.224 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns loader:u1\|load_val\[11\] 1 REG LC_X1_Y17_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y17_N2; Fanout = 1; REG Node = 'loader:u1\|load_val\[11\]'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { loader:u1|load_val[11] } "NODE_NAME" } } { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/loader.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.001 ns) + CELL(0.223 ns) 2.224 ns timer:u2\|counter4:u2\|dual_reg4:u3\|q\[3\] 2 REG LC_X24_Y25_N4 10 " "Info: 2: + IC(2.001 ns) + CELL(0.223 ns) = 2.224 ns; Loc. = LC_X24_Y25_N4; Fanout = 10; REG Node = 'timer:u2\|counter4:u2\|dual_reg4:u3\|q\[3\]'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.224 ns" { loader:u1|load_val[11] timer:u2|counter4:u2|dual_reg4:u3|q[3] } "NODE_NAME" } } { "dual_reg4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/dual_reg4.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.223 ns ( 10.03 % ) " "Info: Total cell delay = 0.223 ns ( 10.03 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.001 ns ( 89.97 % ) " "Info: Total interconnect delay = 2.001 ns ( 89.97 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.224 ns" { loader:u1|load_val[11] timer:u2|counter4:u2|dual_reg4:u3|q[3] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "2.224 ns" { loader:u1|load_val[11] timer:u2|counter4:u2|dual_reg4:u3|q[3] } { 0.000ns 2.001ns } { 0.000ns 0.223ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-7.339 ns - Smallest " "Info: - Smallest clock skew is -7.339 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.921 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.921 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 21 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 21; CLK Node = 'clk'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "microwave_timer.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/microwave_timer.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.551 ns) + CELL(0.542 ns) 2.921 ns timer:u2\|counter4:u2\|dual_reg4:u3\|q\[3\] 2 REG LC_X24_Y25_N4 10 " "Info: 2: + IC(1.551 ns) + CELL(0.542 ns) = 2.921 ns; Loc. = LC_X24_Y25_N4; Fanout = 10; REG Node = 'timer:u2\|counter4:u2\|dual_reg4:u3\|q\[3\]'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.093 ns" { clk timer:u2|counter4:u2|dual_reg4:u3|q[3] } "NODE_NAME" } } { "dual_reg4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/dual_reg4.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 46.90 % ) " "Info: Total cell delay = 1.370 ns ( 46.90 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.551 ns ( 53.10 % ) " "Info: Total interconnect delay = 1.551 ns ( 53.10 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.921 ns" { clk timer:u2|counter4:u2|dual_reg4:u3|q[3] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "2.921 ns" { clk clk~out0 timer:u2|counter4:u2|dual_reg4:u3|q[3] } { 0.000ns 0.000ns 1.551ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 10.260 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 10.260 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 21 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 21; CLK Node = 'clk'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "microwave_timer.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/microwave_timer.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.523 ns) + CELL(0.698 ns) 3.049 ns timer:u2\|counter4:u1\|dual_reg4:u3\|q\[2\] 2 REG LC_X28_Y25_N4 10 " "Info: 2: + IC(1.523 ns) + CELL(0.698 ns) = 3.049 ns; Loc. = LC_X28_Y25_N4; Fanout = 10; REG Node = 'timer:u2\|counter4:u1\|dual_reg4:u3\|q\[2\]'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.221 ns" { clk timer:u2|counter4:u1|dual_reg4:u3|q[2] } "NODE_NAME" } } { "dual_reg4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/dual_reg4.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.401 ns) + CELL(0.366 ns) 3.816 ns timer:u2\|counter4:u1\|zero_detect:u0\|Equal0~14 3 COMB LC_X28_Y25_N5 4 " "Info: 3: + IC(0.401 ns) + CELL(0.366 ns) = 3.816 ns; Loc. = LC_X28_Y25_N5; Fanout = 4; COMB Node = 'timer:u2\|counter4:u1\|zero_detect:u0\|Equal0~14'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.767 ns" { timer:u2|counter4:u1|dual_reg4:u3|q[2] timer:u2|counter4:u1|zero_detect:u0|Equal0~14 } "NODE_NAME" } } { "zero_detect.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/zero_detect.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.788 ns) + CELL(0.280 ns) 4.884 ns state_control:u0\|Selector2~36 4 COMB LC_X24_Y25_N1 8 " "Info: 4: + IC(0.788 ns) + CELL(0.280 ns) = 4.884 ns; Loc. = LC_X24_Y25_N1; Fanout = 8; COMB Node = 'state_control:u0\|Selector2~36'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.068 ns" { timer:u2|counter4:u1|zero_detect:u0|Equal0~14 state_control:u0|Selector2~36 } "NODE_NAME" } } { "state_control.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/state_control.vhd" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.862 ns) + CELL(0.280 ns) 7.026 ns loader:u1\|Mux15~238 5 COMB LC_X1_Y17_N1 16 " "Info: 5: + IC(1.862 ns) + CELL(0.280 ns) = 7.026 ns; Loc. = LC_X1_Y17_N1; Fanout = 16; COMB Node = 'loader:u1\|Mux15~238'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.142 ns" { state_control:u0|Selector2~36 loader:u1|Mux15~238 } "NODE_NAME" } } { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/loader.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.159 ns) + CELL(0.075 ns) 10.260 ns loader:u1\|load_val\[11\] 6 REG LC_X1_Y17_N2 1 " "Info: 6: + IC(3.159 ns) + CELL(0.075 ns) = 10.260 ns; Loc. = LC_X1_Y17_N2; Fanout = 1; REG Node = 'loader:u1\|load_val\[11\]'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.234 ns" { loader:u1|Mux15~238 loader:u1|load_val[11] } "NODE_NAME" } } { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/loader.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.527 ns ( 24.63 % ) " "Info: Total cell delay = 2.527 ns ( 24.63 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.733 ns ( 75.37 % ) " "Info: Total interconnect delay = 7.733 ns ( 75.37 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "10.260 ns" { clk timer:u2|counter4:u1|dual_reg4:u3|q[2] timer:u2|counter4:u1|zero_detect:u0|Equal0~14 state_control:u0|Selector2~36 loader:u1|Mux15~238 loader:u1|load_val[11] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "10.260 ns" { clk clk~out0 timer:u2|counter4:u1|dual_reg4:u3|q[2] timer:u2|counter4:u1|zero_detect:u0|Equal0~14 state_control:u0|Selector2~36 loader:u1|Mux15~238 loader:u1|load_val[11] } { 0.000ns 0.000ns 1.523ns 0.401ns 0.788ns 1.862ns 3.159ns } { 0.000ns 0.828ns 0.698ns 0.366ns 0.280ns 0.280ns 0.075ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.921 ns" { clk timer:u2|counter4:u2|dual_reg4:u3|q[3] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "2.921 ns" { clk clk~out0 timer:u2|counter4:u2|dual_reg4:u3|q[3] } { 0.000ns 0.000ns 1.551ns } { 0.000ns 0.828ns 0.542ns } "" } } { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "10.260 ns" { clk timer:u2|counter4:u1|dual_reg4:u3|q[2] timer:u2|counter4:u1|zero_detect:u0|Equal0~14 state_control:u0|Selector2~36 loader:u1|Mux15~238 loader:u1|load_val[11] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "10.260 ns" { clk clk~out0 timer:u2|counter4:u1|dual_reg4:u3|q[2] timer:u2|counter4:u1|zero_detect:u0|Equal0~14 state_control:u0|Selector2~36 loader:u1|Mux15~238 loader:u1|load_val[11] } { 0.000ns 0.000ns 1.523ns 0.401ns 0.788ns 1.862ns 3.159ns } { 0.000ns 0.828ns 0.698ns 0.366ns 0.280ns 0.280ns 0.075ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/loader.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "dual_reg4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/dual_reg4.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/loader.vhd" 14 -1 0 } } { "dual_reg4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/dual_reg4.vhd" 21 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.224 ns" { loader:u1|load_val[11] timer:u2|counter4:u2|dual_reg4:u3|q[3] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "2.224 ns" { loader:u1|load_val[11] timer:u2|counter4:u2|dual_reg4:u3|q[3] } { 0.000ns 2.001ns } { 0.000ns 0.223ns } "" } } { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.921 ns" { clk timer:u2|counter4:u2|dual_reg4:u3|q[3] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "2.921 ns" { clk clk~out0 timer:u2|counter4:u2|dual_reg4:u3|q[3] } { 0.000ns 0.000ns 1.551ns } { 0.000ns 0.828ns 0.542ns } "" } } { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "10.260 ns" { clk timer:u2|counter4:u1|dual_reg4:u3|q[2] timer:u2|counter4:u1|zero_detect:u0|Equal0~14 state_control:u0|Selector2~36 loader:u1|Mux15~238 loader:u1|load_val[11] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "10.260 ns" { clk clk~out0 timer:u2|counter4:u1|dual_reg4:u3|q[2] timer:u2|counter4:u1|zero_detect:u0|Equal0~14 state_control:u0|Selector2~36 loader:u1|Mux15~238 loader:u1|load_val[11] } { 0.000ns 0.000ns 1.523ns 0.401ns 0.788ns 1.862ns 3.159ns } { 0.000ns 0.828ns 0.698ns 0.366ns 0.280ns 0.280ns 0.075ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 140 " "Warning: Circuit may not operate. Detected 140 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}