microwave_timer.tan.qmsg

该芯片的功能是： ① 有一复位开关

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "microwave_timer.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/microwave_timer.vhd" 5 -1 0 } } { "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "test " "Info: Assuming node \"test\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "microwave_timer.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/microwave_timer.vhd" 8 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "set_time " "Info: Assuming node \"set_time\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "microwave_timer.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/microwave_timer.vhd" 9 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "30 " "Warning: Found 30 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "loader:u1\|Mux15~238 " "Info: Detected gated clock \"loader:u1\|Mux15~238\" as buffer" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/loader.vhd" 21 -1 0 } } { "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "loader:u1\|Mux15~238" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "state_control:u0\|current_state.lamp_test " "Info: Detected ripple clock \"state_control:u0\|current_state.lamp_test\" as buffer" {  } { { "state_control.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/state_control.vhd" 22 -1 0 } } { "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "state_control:u0\|current_state.lamp_test" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "state_control:u0\|current_state.set_clock " "Info: Detected ripple clock \"state_control:u0\|current_state.set_clock\" as buffer" {  } { { "state_control.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/state_control.vhd" 22 -1 0 } } { "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "state_control:u0\|current_state.set_clock" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "timer:u2\|counter4:u1\|dual_reg4:u3\|q\[1\] " "Info: Detected ripple clock \"timer:u2\|counter4:u1\|dual_reg4:u3\|q\[1\]\" as buffer" {  } { { "dual_reg4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/dual_reg4.vhd" 21 -1 0 } } { "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "timer:u2\|counter4:u1\|dual_reg4:u3\|q\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "timer:u2\|counter4:u1\|dual_reg4:u3\|q\[2\] " "Info: Detected ripple clock \"timer:u2\|counter4:u1\|dual_reg4:u3\|q\[2\]\" as buffer" {  } { { "dual_reg4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/dual_reg4.vhd" 21 -1 0 } } { "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "timer:u2\|counter4:u1\|dual_reg4:u3\|q\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "timer:u2\|counter4:u1\|dual_reg4:u3\|q\[0\] " "Info: Detected ripple clock \"timer:u2\|counter4:u1\|dual_reg4:u3\|q\[0\]\" as buffer" {  } { { "dual_reg4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/dual_reg4.vhd" 21 -1 0 } } { "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "timer:u2\|counter4:u1\|dual_reg4:u3\|q\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "timer:u2\|counter4:u0\|dual_reg4:u3\|q\[3\] " "Info: Detected ripple clock \"timer:u2\|counter4:u0\|dual_reg4:u3\|q\[3\]\" as buffer" {  } { { "dual_reg4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/dual_reg4.vhd" 21 -1 0 } } { "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "timer:u2\|counter4:u0\|dual_reg4:u3\|q\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "timer:u2\|counter4:u0\|zero_detect:u0\|Equal0~14 " "Info: Detected gated clock \"timer:u2\|counter4:u0\|zero_detect:u0\|Equal0~14\" as buffer" {  } { { "zero_detect.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/zero_detect.vhd" 9 -1 0 } } { "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "timer:u2\|counter4:u0\|zero_detect:u0\|Equal0~14" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "timer:u2\|counter4:u0\|dual_reg4:u3\|q\[1\] " "Info: Detected ripple clock \"timer:u2\|counter4:u0\|dual_reg4:u3\|q\[1\]\" as buffer" {  } { { "dual_reg4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/dual_reg4.vhd" 21 -1 0 } } { "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "timer:u2\|counter4:u0\|dual_reg4:u3\|q\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "timer:u2\|done~43 " "Info: Detected gated clock \"timer:u2\|done~43\" as buffer" {  } { { "timer.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/timer.vhd" 9 -1 0 } } { "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "timer:u2\|done~43" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "timer:u2\|counter4:u1\|zero_detect:u0\|Equal0~14 " "Info: Detected gated clock \"timer:u2\|counter4:u1\|zero_detect:u0\|Equal0~14\" as buffer" {  } { { "zero_detect.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/zero_detect.vhd" 9 -1 0 } } { "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "timer:u2\|counter4:u1\|zero_detect:u0\|Equal0~14" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "timer:u2\|counter4:u0\|dual_reg4:u3\|q\[0\] " "Info: Detected ripple clock \"timer:u2\|counter4:u0\|dual_reg4:u3\|q\[0\]\" as buffer" {  } { { "dual_reg4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/dual_reg4.vhd" 21 -1 0 } } { "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "timer:u2\|counter4:u0\|dual_reg4:u3\|q\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "timer:u2\|counter4:u0\|dual_reg4:u3\|q\[2\] " "Info: Detected ripple clock \"timer:u2\|counter4:u0\|dual_reg4:u3\|q\[2\]\" as buffer" {  } { { "dual_reg4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/dual_reg4.vhd" 21 -1 0 } } { "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "timer:u2\|counter4:u0\|dual_reg4:u3\|q\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "timer:u2\|counter4:u2\|dual_reg4:u3\|q\[1\] " "Info: Detected ripple clock \"timer:u2\|counter4:u2\|dual_reg4:u3\|q\[1\]\" as buffer" {  } { { "dual_reg4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/dual_reg4.vhd" 21 -1 0 } } { "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "timer:u2\|counter4:u2\|dual_reg4:u3\|q\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "timer:u2\|counter4:u1\|dual_reg4:u3\|q\[3\] " "Info: Detected ripple clock \"timer:u2\|counter4:u1\|dual_reg4:u3\|q\[3\]\" as buffer" {  } { { "dual_reg4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/dual_reg4.vhd" 21 -1 0 } } { "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "timer:u2\|counter4:u1\|dual_reg4:u3\|q\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "timer:u2\|counter4:u2\|dual_reg4:u3\|q\[0\] " "Info: Detected ripple clock \"timer:u2\|counter4:u2\|dual_reg4:u3\|q\[0\]\" as buffer" {  } { { "dual_reg4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/dual_reg4.vhd" 21 -1 0 } } { "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "timer:u2\|counter4:u2\|dual_reg4:u3\|q\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "timer:u2\|counter4:u2\|dual_reg4:u3\|q\[2\] " "Info: Detected ripple clock \"timer:u2\|counter4:u2\|dual_reg4:u3\|q\[2\]\" as buffer" {  } { { "dual_reg4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/dual_reg4.vhd" 21 -1 0 } } { "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "timer:u2\|counter4:u2\|dual_reg4:u3\|q\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "timer:u2\|counter4:u3\|decr4:u2\|Equal0~23 " "Info: Detected gated clock \"timer:u2\|counter4:u3\|decr4:u2\|Equal0~23\" as buffer" {  } { { "d:/program files/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/program files/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1837 -1 0 } } { "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "timer:u2\|counter4:u3\|decr4:u2\|Equal0~23" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "timer:u2\|counter4:u3\|dual_reg4:u3\|q\[1\] " "Info: Detected ripple clock \"timer:u2\|counter4:u3\|dual_reg4:u3\|q\[1\]\" as buffer" {  } { { "dual_reg4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/dual_reg4.vhd" 21 -1 0 } } { "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "timer:u2\|counter4:u3\|dual_reg4:u3\|q\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "timer:u2\|counter4:u3\|dual_reg4:u3\|q\[0\] " "Info: Detected ripple clock \"timer:u2\|counter4:u3\|dual_reg4:u3\|q\[0\]\" as buffer" {  } { { "dual_reg4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/dual_reg4.vhd" 21 -1 0 } } { "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "timer:u2\|counter4:u3\|dual_reg4:u3\|q\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "timer:u2\|counter4:u2\|zero_detect:u0\|Equal0~14 " "Info: Detected gated clock \"timer:u2\|counter4:u2\|zero_detect:u0\|Equal0~14\" as buffer" {  } { { "zero_detect.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/zero_detect.vhd" 9 -1 0 } } { "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "timer:u2\|counter4:u2\|zero_detect:u0\|Equal0~14" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "timer:u2\|counter4:u2\|dual_reg4:u3\|q\[3\] " "Info: Detected ripple clock \"timer:u2\|counter4:u2\|dual_reg4:u3\|q\[3\]\" as buffer" {  } { { "dual_reg4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/dual_reg4.vhd" 21 -1 0 } } { "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "timer:u2\|counter4:u2\|dual_reg4:u3\|q\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "loader:u1\|Mux15~237 " "Info: Detected gated clock \"loader:u1\|Mux15~237\" as buffer" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/loader.vhd" 21 -1 0 } } { "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "loader:u1\|Mux15~237" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "state_control:u0\|Selector2~36 " "Info: Detected gated clock \"state_control:u0\|Selector2~36\" as buffer" {  } { { "state_control.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/state_control.vhd" 40 -1 0 } } { "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "state_control:u0\|Selector2~36" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "state_control:u0\|Selector1~63 " "Info: Detected gated clock \"state_control:u0\|Selector1~63\" as buffer" {  } { { "state_control.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/state_control.vhd" 40 -1 0 } } { "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "state_control:u0\|Selector1~63" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "state_control:u0\|current_state.done_msg " "Info: Detected ripple clock \"state_control:u0\|current_state.done_msg\" as buffer" {  } { { "state_control.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/state_control.vhd" 22 -1 0 } } { "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "state_control:u0\|current_state.done_msg" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "timer:u2\|counter4:u3\|dual_reg4:u3\|q\[2\] " "Info: Detected ripple clock \"timer:u2\|counter4:u3\|dual_reg4:u3\|q\[2\]\" as buffer" {  } { { "dual_reg4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/dual_reg4.vhd" 21 -1 0 } } { "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "timer:u2\|counter4:u3\|dual_reg4:u3\|q\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "timer:u2\|counter4:u3\|dual_reg4:u3\|q\[3\] " "Info: Detected ripple clock \"timer:u2\|counter4:u3\|dual_reg4:u3\|q\[3\]\" as buffer" {  } { { "dual_reg4.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/dual_reg4.vhd" 21 -1 0 } } { "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "timer:u2\|counter4:u3\|dual_reg4:u3\|q\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "state_control:u0\|current_state.timer " "Info: Detected ripple clock \"state_control:u0\|current_state.timer\" as buffer" {  } { { "state_control.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/state_control.vhd" 22 -1 0 } } { "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "state_control:u0\|current_state.timer" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "state_control:u0\|current_state.idle " "Info: Detected ripple clock \"state_control:u0\|current_state.idle\" as buffer" {  } { { "state_control.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/state_control.vhd" 22 -1 0 } } { "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "state_control:u0\|current_state.idle" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}