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📄 mux_ldc.tdf

📁 该芯片的功能是: ① 有一复位开关
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--lpm_mux CASCADE_CHAIN="IGNORE" DEVICE_FAMILY="Stratix" IGNORE_CASCADE_BUFFERS="ON" LPM_SIZE=8 LPM_WIDTH=1 LPM_WIDTHS=3 data result sel
--VERSION_BEGIN 7.0 cbx_lpm_mux 2006:04:25:15:10:08:SJ cbx_mgl 2006:10:27:16:08:48:SJ  VERSION_END


--  Copyright (C) 1991-2007 Altera Corporation
--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files from any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
--  Altera or its authorized distributors.  Please refer to the 
--  applicable agreement for further details.



--synthesis_resources = lut 5 
SUBDESIGN mux_ldc
( 
	data[7..0]	:	input;
	result[0..0]	:	output;
	sel[2..0]	:	input;
) 
VARIABLE 
	result_node[0..0]	: WIRE;
	sel_ffs_wire[2..0]	: WIRE;
	sel_node[2..0]	: WIRE;
	w_data38w[3..0]	: WIRE;
	w_data39w[3..0]	: WIRE;
	w_data9w[7..0]	: WIRE;
	w_result36w	: WIRE;
	w_result37w	: WIRE;
	w_result44w	: WIRE;
	w_result65w	: WIRE;
	w_sel40w[1..0]	: WIRE;

BEGIN 
	result[] = result_node[];
	result_node[] = ( ((sel_node[2..2] & w_result37w) # ((! sel_node[2..2]) & w_result36w)));
	sel_ffs_wire[] = ( sel[2..0]);
	sel_node[] = ( sel_ffs_wire[2..2], sel[1..0]);
	w_data38w[3..0] = w_data9w[3..0];
	w_data39w[3..0] = w_data9w[7..4];
	w_data9w[] = ( data[7..0]);
	w_result36w = (((w_data38w[1..1] & w_sel40w[0..0]) & (! w_result44w)) # (w_result44w & (w_data38w[3..3] # (! w_sel40w[0..0]))));
	w_result37w = (((w_data39w[1..1] & w_sel40w[0..0]) & (! w_result65w)) # (w_result65w & (w_data39w[3..3] # (! w_sel40w[0..0]))));
	w_result44w = (((w_data38w[0..0] & (! w_sel40w[1..1])) & (! w_sel40w[0..0])) # (w_sel40w[1..1] & (w_sel40w[0..0] # w_data38w[2..2])));
	w_result65w = (((w_data39w[0..0] & (! w_sel40w[1..1])) & (! w_sel40w[0..0])) # (w_sel40w[1..1] & (w_sel40w[0..0] # w_data39w[2..2])));
	w_sel40w[1..0] = sel_node[1..0];
END;
--VALID FILE

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