microwave_timer.map.qmsg

该芯片的功能是： ① 有一复位开关

{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "load_val\[4\] loader.vhd(14) " "Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for \"load_val\[4\]\"" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/loader.vhd" 14 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "load_val\[5\] loader.vhd(14) " "Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for \"load_val\[5\]\"" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/loader.vhd" 14 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "load_val\[6\] loader.vhd(14) " "Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for \"load_val\[6\]\"" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/loader.vhd" 14 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "load_val\[7\] loader.vhd(14) " "Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for \"load_val\[7\]\"" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/loader.vhd" 14 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "load_val\[8\] loader.vhd(14) " "Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for \"load_val\[8\]\"" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/loader.vhd" 14 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "load_val\[9\] loader.vhd(14) " "Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for \"load_val\[9\]\"" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/loader.vhd" 14 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "load_val\[10\] loader.vhd(14) " "Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for \"load_val\[10\]\"" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/loader.vhd" 14 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "load_val\[11\] loader.vhd(14) " "Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for \"load_val\[11\]\"" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/loader.vhd" 14 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "load_val\[12\] loader.vhd(14) " "Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for \"load_val\[12\]\"" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/loader.vhd" 14 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "load_val\[13\] loader.vhd(14) " "Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for \"load_val\[13\]\"" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/loader.vhd" 14 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "load_val\[14\] loader.vhd(14) " "Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for \"load_val\[14\]\"" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/loader.vhd" 14 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "load_val\[15\] loader.vhd(14) " "Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for \"load_val\[15\]\"" {  } { { "loader.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/loader.vhd" 14 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "timer timer:u2 " "Info: Elaborating entity \"timer\" for hierarchy \"timer:u2\"" {  } { { "microwave_timer.vhd" "u2" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/microwave_timer.vhd" 65 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter4 timer:u2\|counter4:u3 " "Info: Elaborating entity \"counter4\" for hierarchy \"timer:u2\|counter4:u3\"" {  } { { "timer.vhd" "u3" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/timer.vhd" 56 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "zero_detect timer:u2\|counter4:u3\|zero_detect:u0 " "Info: Elaborating entity \"zero_detect\" for hierarchy \"timer:u2\|counter4:u3\|zero_detect:u0\"" {  } { { "counter4.vhd" "u0" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/counter4.vhd" 38 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bcd7 timer:u2\|counter4:u3\|bcd7:u1 " "Info: Elaborating entity \"bcd7\" for hierarchy \"timer:u2\|counter4:u3\|bcd7:u1\"" {  } { { "counter4.vhd" "u1" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/counter4.vhd" 40 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decr4 timer:u2\|counter4:u3\|decr4:u2 " "Info: Elaborating entity \"decr4\" for hierarchy \"timer:u2\|counter4:u3\|decr4:u2\"" {  } { { "counter4.vhd" "u2" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/counter4.vhd" 42 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dual_reg4 timer:u2\|counter4:u3\|dual_reg4:u3 " "Info: Elaborating entity \"dual_reg4\" for hierarchy \"timer:u2\|counter4:u3\|dual_reg4:u3\"" {  } { { "counter4.vhd" "u3" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/counter4.vhd" 44 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|microwave_timer\|state_control:u0\|current_state 5 " "Info: State machine \"\|microwave_timer\|state_control:u0\|current_state\" contains 5 states" {  } { { "state_control.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/state_control.vhd" 22 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|microwave_timer\|state_control:u0\|current_state " "Info: Selected Auto state machine encoding method for state machine \"\|microwave_timer\|state_control:u0\|current_state\"" {  } { { "state_control.vhd" "" { Text "D:/Program Files/altera/70/quartus/自己实践/微波炉定时器芯片/整个系统/state_control.vhd" 22 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0}