dual_reg4.vhd

来自「该芯片的功能是： ① 有一复位开关」· VHDL 代码 · 共 22 行

library ieee;
use ieee.std_logic_1164.all;
entity dual_reg4 is
   port(a:in std_logic_vector(3 downto 0);
        b:in std_logic_vector(3 downto 0);
        clk:in std_logic;
        lda:in std_logic;
        ldb:in std_logic;
        q:out std_logic_vector(3 downto 0));
end dual_reg4;
architecture rtl of dual_reg4 is
begin
    process
    begin
      wait until clk'event and clk='1';
      if (lda='1') then
          q<=a;
      elsif(ldb='1') then
          q<=b;
      end if;
    end process;
end rtl;