decr4.vhd

来自「该芯片的功能是： ① 有一复位开关」· VHDL 代码 · 共 14 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity decr4 is
  port(cnt_f_5:in std_logic;
       dec_in: in std_logic_vector(3 downto 0);
       dec_out:out std_logic_vector(3 downto 0));
end decr4;
architecture rtl of decr4 is  
   signal maxval:std_logic_vector(3 downto 0);
begin
   maxval<="0101" when cnt_f_5='1' else "1001";
   dec_out<=maxval when (unsigned(dec_in)=0) else unsigned(dec_in)-1;
end rtl;